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XR16V794
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL
MAY 2007 REV. 1.0.0
GENERAL DESCRIPTION
The XR16V7941 (794), is a 2.25V to 3.6V octal Universal Asynchronous Receiver and Transmitter (UART) with 5V tolerant serial (modem) inputs. The highly integrated device is designed for high bandwidth requirement in communication systems. The global interrupt source register provides a complete interrupt status indication for all 4 channels to speed up interrupt parsing. Each UART has its own 16C550 compatible set of configuration registers, TX and RX FIFOs of 64 bytes, fully programmable transmit and receive FIFO trigger levels, TX and RX FIFO level counters, automatic RTS/CTS or DTR/ DSR hardware flow control with programmable hysteresis, autoamtic software (Xon/Xoff) flow control, RS-485 half-duplex direction control with programmable turn-around delay, Intel or Motorola bus interface and sleep mode with a wake-up indicator.
NOTE: Covered by US patents #5,649,122 and #5,949,787
FEATURES
* 2.25V to 3.6V with 5V Tolerant Serial Inputs * Single Interrupt output for all 4 UARTs * A Global Interrupt Source Register for all 4 UARTs * 5G "Flat" UART Registers for easier programming * Simultaneous Initialization of all UART channels * A General Purpose Command-driven 16-bit
Timer/counter
* Sleep Mode with Wake-up Indication * Highly Integrated Device for Space Saving * Each UART is independently controlled with:

APPLICATIONS
* Remote Access Servers * Ethernet Network to Serial Ports * Network Management * Factory Automation and Process Control * Point-of-Sale Systems * Multi-port RS-232/RS-422/RS-485 Cards
FIGURE 1. BLOCK DIAGRAM
16C550 Compatible 5G Register Set 64-byte Transmit and Receive FIFOs Fractional Baud Rate Generator Transmit and Receive FIFO Level Counters Programmable TX and RX FIFO Trigger Level Automatic RTS/CTS or DTR/DSR Flow Control Automatic Xon/Xoff Software Flow Control RS485 Half-Duplex Control Output with Selectable Turn-around Delay Infrared (IrDA 1.0) Data Encoder/Decoder Programmable Data Rate with Prescaler
* Up to 8 Mbps Serial Data Rate * Pin compatible to XR16L784. Same 64-pin LQFP
Package (10x10x1.4 mm)
*All Inputs are 5V Tolerant (Except XTAL1) UART Channel 0 A7:A0 D7:D0 IOR# IOW# CS# INT# 16/68# RST# ENIR Crystal Osc/ Buffer 16-bit Timer/Counter UART Channel 3 Intel or Motorola Data Bus Interface Device Configuration Register s
BRG UART Regs 64 Byte TX FIFO TX & RX IR ENDEC
2.25V to 3.6V VCC GND
TX0, RX0, DTR0#, DSR0#, RTS0#, CTS0#, CD0#, RI0#
64 Byte RX FIFO
UART Channel 1
UART Channel 2 TX3, RX3, DTR3#, DSR3#, RTS3#, CTS3#, CD3#, RI3# XTAL1 XTAL2 TMRCK
Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com
XR16V794
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
REV. 1.0.0
FIGURE 2. PIN OUT OF THE DEVICE
TX1 DTR1# RTS1# RI1# CD1# DSR1# CTS1# RX1 TX2 DTR2# RTS2# RI2# CD2# DSR2# CTS2# RX2 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
XTAL2 XTAL1 GND VCC TX0 DTR0# RTS0# RI0# CD0# DSR0# CTS0# RX0 INT# CS# A0 A1
XR16V794 64-TQFP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A2 A3 A4 A5 A6 A7 IOR# IOW# VCC GND D0 D1 D2 D3 D4 D5
ENIR TMRCK VCC GND TX3 DTR3# RTS3# RI3# CD3# DSR3# CTS3# RX3 RST# 16/68# D7 D6
ORDERING INFORMATION
PART NUMBER XR16V794IV PACKAGE 64-Lead LQFP OPERATING TEMPERATURE RANGE -40C to +85C DEVICE STATUS Active
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
2
XR16V794
REV. 1.0.0
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
PIN DESCRIPTIONS
NAME
PIN #
TYPE
DESCRIPTION
DATA BUS INTERFACE A7-A0 6-1,64,63 I Address data lines [7:0]. A0:A3 selects individual UART's 16 configuration registers, A4:A6 selects UART channel 0 to 3, and A7 selects the global device configuration registers Data bus lines [7:0] (bidirectional). When 16/68# pin is HIGH, it selects Intel bus interface and this input is read strobe (active low). The falling edge instigates an internal read cycle and retrieves the data byte from an internal register pointed by the address lines [A7:A0], puts it on the data bus to allow the host processor to read it on the leading edge. When 16/68# pin is LOW, it selects Motorola bus interface and this input should be connected to VCC. When 16/68# pin is HIGH, it selects Intel bus interface and this input becomes write strobe (active low). The falling edge instigates the internal write cycle and the leading edge transfers the data byte on the data bus to an internal register pointed by the address lines. When 16/68# pin is LOW, it selects Motorola bus interface and this input becomes read (logic 1) and write (logic 0) signal. When 16/68# pin is HIGH, this input is chip select (active low) to enable the XR16V794 device. When 16/68# pin is LOW, this input becomes the read and write strobe (active low) for the Motorola bus interface. Global interrupt output from XR16V794 (open drain, active low). This output requires an external pull-up resistor (47K-100K ohms) to operate properly. It may be shared with other devices in the system to form a single interrupt line to the host processor and have the software driver polls each device for the interrupt status.
D7:D0 IOR#
18-11 7
IO I
IOW# (R/W#)
8
I
CS#
62
I
INT#
61
OD
MODEM OR SERIAL I/O INTERFACE TX0 RX0 53 60 O I UART channel 0 Transmit Data or infrared transmit data. Normal TXD output idles HIGH while infrared TXD output idles LOW. UART channel 0 Receive Data or infrared receive data. Normal RXD input idles HIGH while infrared RXD input idles LOW. In the infrared mode, the polarity of the incoming RXD signal can be selected via FCTR bit-4. If this bit is a logic 0, a LOW on the RXD input is considered a mark and if this bit is a logic 1, a HIGH on the RXD input is considered a space. UART channel 0 Request to Send or general purpose output (active low). This port must be asserted prior using for one of two functions: 1) auto RTS flow control, see EFR bit-6, MCR bits-1 & 2, FCTR bits 0-3 and IER bit-6 2) Auto RS485 half-duplex direction control, see FCTR bit-5, MCR bit-2 and MSR bits 4-7. UART channel 0 Clear to Send or general purpose input (active low). It can be used for auto CTS flow control, see EFR bit-7, MCR bit-2 and IER bit-7.
RTS0#
55
O
CTS0#
59
I
3
XR16V794
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
REV. 1.0.0
NAME DTR0#
PIN # 54
TYPE O
DESCRIPTION UART channel 0 Data Terminal Ready or general purpose output (active low). This port must be asserted prior using for one of two functions: 1) auto DTR flow control, see EFR bit-6, FCTR bits-0 to 3, MCR bits-0 & 2, and IER bit-6 2) Auto RS485 half-duplex direction control, see FCTR bit-5, MCR bit-2 and MSR bit 4-7. UART channel 0 Data Set Ready or general purpose input (active low). It can be used for auto DSR flow control, see EFR bit-7, MCR bit-2 and IER bit-7. UART channel 0 Carrier Detect or general purpose input (active low). UART channel 0 Ring Indicator or general purpose input (active low). UART channel 1 Transmit Data or infrared transmit data. Normal TXD output idles HIGH while infrared TXD output idles LOW. UART channel 1 Receive Data or infrared receive data. Normal RXD input idles HIGH while infrared RXD input idles LOW. In the infrared mode, the polarity of the incoming RXD signal can be selected via FCTR bit-4. If this bit is a logic 0, a LOW on the RXD input is considered a mark and if this bit is a logic 1, a HIGH on the RXD input is considered a space. UART channel 1 Request to Send or general purpose output (active low). See description of RTS0# pin. UART channel 1 Clear to Send or general purpose input (active low). See description of CTS0# pin. UART channel 1 Data Terminal Ready or general purpose output (active low). See description of DTS0# pin. UART channel 1 Data Set Ready or general purpose input (active low). See description of DSR0# pin. UART channel 1 Carrier Detect or general purpose input (active low). UART channel 1 Ring Indicator or general purpose input (active low). UART channel 2 Transmit Data or infrared transmit data. Normal TXD output idles HIGH while infrared TXD output idles LOW. UART channel 2 Receive Data or infrared receive data. Normal RXD input idles HIGH while infrared RXD input idles LOW. In the infrared mode, the polarity of the incoming RXD signal can be selected via FCTR bit-4. If this bit is a logic 0, a LOW on the RXD input is considered a mark and if this bit is a logic 1, a HIGH on the RXD input is considered a space. UART channel 2 Request to Send or general purpose output (active low). See description of RTS0# pin. UART channel 2 Clear to Send or general purpose input (active low). See description of CTS0# pin. UART channel 2 Data Terminal Ready or general purpose output (active low). See description of DTS0# pin. UART channel 2 Data Set Ready or general purpose input (active low). See description of DSR0# pin. UART channel 2 Carrier Detect or general purpose input (active low). UART channel 2 Ring Indicator or general purpose intput (active low).
DSR0# CD0# RI0# TX1 RX1
58 57 56 48 41
I I I O I
RTS1# CTS1# DTR1# DSR1# CD1# RI1# TX2 RX2
46 42 47 43 44 45 40 33
O I O I I I O I
RTS2# CTS2# DTR2# DSR2# CD2# RI2#
38 34 39 35 36 37
O I O I I I
4
XR16V794
REV. 1.0.0
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
NAME TX3 RX3
PIN # 28 21
TYPE O I
DESCRIPTION UART channel 3 Transmit Data or infrared transmit data. Normal TXD output idles HIGH while infrared TXD output idles LOW. UART channel 3 Receive Data or infrared receive data. Normal RXD input idles HIGH while infrared RXD input idles LOW. In the infrared mode, the polarity of the incoming RXD signal can be selected via FCTR bit-4. If this bit is a logic 0, a LOW on the RXD input is considered a mark and if this bit is a logic 1, a HIGH on the RXD input is considered a space. UART channel 3 Request to Send or general purpose output (active low). See description of RTS0# pin. UART channel 3 Clear to Send or general purpose input (active low).d. See description of CTS0# pin. UART channel 3 Data Terminal Ready or general purpose output (active low). See description of DTS0# pin. UART channel 3 Data Set Ready or general purpose input (active low). See description of DSR0# pin. UART channel 3 Carrier Detect or general purpose input (active low). UART channel 3 Ring Indicator or general purpose input (active low).
RTS3# CTS3# DTR3# DSR3# CD3# RI3#
26 22 27 23 24 25
O I O I I I
ANCILLARY SIGNALS XTAL1 XTAL2 TMRCK ENIR 50 49 31 32 I O I I Crystal or external clock input. Caution: this input is not 5V tolerant. Crystal or buffered clock output. 16-bit timer/counter external clock input. Infrared mode enable (active high). This pin is sampled during power up, following a hardware reset (RST#) or soft-reset (register RESET). It can be used to start up all 4 UARTs in the infrared mode. The sampled logic state is transferred to MCR bit6 in the UART. Reset (active low). The configuration and UART registers are reset to default values, see Table 19. Intel or Motorola data bus interface select. HIGH selects Intel bus interface and LOW selects Motorola interface. This input affects the functionality of IOR#, IOW# and CS# pins. +2.25V to 3.6V supply with 5V tolerant serial (modem) inputs. Power supply common, ground.
RST#
20
I
16/68#
19
I
VCC GND
9,30,52 10,29,51
NOTE: Pin type: I=Input, O=Output, IO= Input/output, OD=Output Open Drain.
5
XR16V794
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE 1.0 DESCRIPTION The XR16V794 (794) integrates the functions of 4 enhanced 16550 UARTs, a general purpose 16-bit timer/ counter and an on-chip oscillator. The device configuration registers include a set of four consecutive interrupt source registers that provides interrupt-status for all 4 UARTs, timer/counter and a sleep wake up indicator. Each UART channel has its own 16550 UART compatible configuration register set for individual channel control, status, and data transfer. Additionally, each UART channel has 64-byte of transmit and receive FIFOs, automatic RTS/CTS or DTR/DSR hardware flow control with hysteresis control, automatic Xon/Xoff and special character software flow control, programmable transmit and receive FIFO trigger levels, FIFO level counters, infrared encoder and decoder (IrDA ver. 1.0), programmable baud rate generator with a prescaler of divide by 1 or 4, and data rate up to 8Mbps with 8X sampling clock or 4Mbps with 16X sampling clock. The XR16V794 is a 2.25-3.6V device with 5 volt tolerant inputs (except XTAL1). 2.0 FUNCTIONAL DESCRIPTIONS 2.1 2.1.1 Device Reset Hardware Reset
REV. 1.0.0
The RST# input resets the internal registers and the serial interface outputs in all 4 channels to their default state (see Table 19). A LOW pulse of longer than 40 ns duration will be required to activate the reset function in the device. 2.1.2 Software Reset The internal registers of each UART can be reset by writing to the RESET register in the Device Configuration Registers. For more details, see the RESET register description on page 24. 2.2 UART Channel Selection A LOW on the chip select pin, CS#, allows the user to select one of the UART channels to configure, send transmit data and/or unload receive data to/from the UART. When address line A7 = 0, address lines A6:A4 are used to select one of the eight channels. See Table 1 below for UART channel selection. TABLE 1: UART CHANNEL SELECTION
A7 0 0 0 0 A6 0 0 0 0 A5 0 0 1 1 A4 0 1 0 1 FUNCTION Channel 0 Selected Channel 1 Selected Channel 2 Selected Channel 3 Selected
2.3
Simultaneous Write to All Channels
During a write cycle, the setting of the Device Configuration register REGB (See Table 8) bit-0 to a logic 1 will override the channel selection of address A6:A4 and allow a simultaneous write to all 4 UART channels when any channel is written to. This functional capability allow the registers in all 4 UART channels to be modified concurrently, saving individual channel initialization time. Caution should be considered, however, when using this capability. Any in-process serial data transfer may be disrupted by changing an active channel's mode. Also, REGB bit-0 should be reset to a logic 0 before attempting to read from the UART.
6
XR16V794
REV. 1.0.0
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
2.4
INT# Ouput
The INT# interrupt output changes according to the operating mode and enhanced features setup. Table 2 and 3 summarize the operating behavior for the transmitter and receiver. TABLE 2: INT# PIN OPERATION FOR TRANSMITTER
Auto RS485 Mode NO FCR BIT-0 = 0 (FIFO DISABLED) HIGH = a byte in THR LOW = THR empty FCR BIT-0 = 1 (FIFO ENABLED) HIGH = FIFO above trigger level LOW = FIFO below trigger level or FIFO empty
YES
HIGH = a byte in THR HIGH = FIFO above trigger level LOW = transmitter empty LOW = FIFO below trigger level or transmitter empty
TABLE 3: INT# PIN OPERATION FOR RECEIVER
FCR BIT-0 = 0 (FIFO DISABLED) HIGH = no data LOW = 1 byte FCR BIT-0 = 1 (FIFO ENABLED) HIGH = FIFO below trigger level LOW = FIFO above trigger level
2.5
CRYSTAL OSCILLATOR / BUFFER
The 794 includes an on-chip oscillator. The crystal oscillator provides the system clock to the Baud Rate Generators (BRG) in each of the 4 UARTs, the 16-bit general purpose timer/counter and internal logics. XTAL1 is the input to the oscillator or external clock buffer input with XTAL2 pin being the output. For programming details, see "Section 2.6, Programmable Baud Rate Generator with Fractional Divisor" on page 8. The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant, fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequency tolerance) connected externally between the XTAL1 and XTAL2 pins (see Figure 3). Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal 4 baud rate generators for standard or custom rates. The typical oscillator connections are shown in Figure 3. For further reading on oscillator circuit please see application note DAN108 on EXAR's web site. FIGURE 3. TYPICAL OSCILLATOR CONNECTIONS
R=300K to 400K
XTAL1 24 MHz C1 22-47pF
XTAL2
C2 22-47pF
7
XR16V794
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE 2.6 Programmable Baud Rate Generator with Fractional Divisor
REV. 1.0.0
Each UART has its own Baud Rate Generator (BRG) with a prescaler for the transmitter and receiver. The prescaler is controlled by a software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide the input crystal or external clock by 1 or 4. The output of the prescaler clocks to the BRG. The BRG further divides this clock by a programmable divisor between 1 and (216 - 0.0625) in increments of 0.0625 (1/16) to obtain a 16X or 8X sampling clock of the serial data rate. The sampling clock is used by the transmitter for data bit shifting and receiver for data sampling. The BRG divisor (DLL, DLM and DLD registers) defaults to the value of '1' (DLL = 0x01, DLM = 0x00 and DLD = 0x00) upon reset. Therefore, the BRG must be programmed during initialization to the operating data rate. The DLL and DLM registers provide the integer part of the divisor and the DLD register provides the fractional part of the dvisior. Only the four lower bits of the DLD are implemented and they are used to select a value from 0 (for setting 0000) to 0.9375 or 15/16 (for setting 1111). Programming the Baud Rate Generator Registers DLL, DLM and DLD provides the capability for selecting the operating data rate. Table 4 shows the standard data rates available with a 24MHz crystal or external clock at 16X clock rate. If the pre-scaler is used (MCR bit-7 = 1), the output data rate will be 4 times less than that shown in Table 4. At 8X sampling rate, these data rates would double. Also, when using 8X sampling mode, please note that the bittime will have a jitter (+/- 1/16) whenever the DLD is non-zero and is an odd number. When using a nonstandard data rate crystal or external clock, the divisor value can be calculated with the following equation(s):
Required Divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16), WITH 8XMODE [7:0] IS 0 Required Divisor (decimal) = (XTAL1 clock frequency / prescaler / (serial data rate x 8), WITH 8XMODE [7:0] IS 1
The closest divisor that is obtainable in the 794 can be calculated using the following formula: ROUND( (Required Divisor - TRUNC(Required Divisor) )*16)/16 + TRUNC(Required Divisor), where
DLM = TRUNC(Required Divisor) >> 8 DLL = TRUNC(Required Divisor) & 0xFF DLD = ROUND( (Required Divisor-TRUNC(Required Divisor) )*16)
In the formulas above, please note that: TRUNC (N) = Integer Part of N. For example, TRUNC (5.6) = 5. ROUND (N) = N rounded towards the closest integer. For example, ROUND (7.3) = 7 and ROUND (9.9) = 10. A >> B indicates right shifting the value 'A' by 'B' number of bits. For example, 0x78A3 >> 8 = 0x0078.
FIGURE 4. BAUD RATE GENERATOR
To Other Channels
DLL, DLM and DLD Registers Prescaler Divide by 1 XTAL1 XTAL2 Crystal Osc/ Buffer Prescaler Divide by 4 MCR Bit-7=0 (default) Fractional Baud Rate Generator Logic MCR Bit-7=1
16X or 8X Sampling Rate Clock to Transmitter and Receiver
8
XR16V794
REV. 1.0.0
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
TABLE 4: TYPICAL DATA RATES WITH A 24 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING
Required Output Data Rate 400 2400 4800 9600 10000 19200 25000 28800 38400 50000 57600 75000 100000 115200 153600 200000 225000 230400 250000 300000 400000 460800 500000 750000 921600 1000000 DIVISOR FOR 16x Clock (Decimal) 3750 625 312.5 156.25 150 78.125 60 52.0833 39.0625 30 26.0417 20 15 13.0208 9.7656 7.5 6.6667 6.5104 6 5 3.75 3.2552 3 2 1.6276 1.5 DIVISOR OBTAINABLE IN 794 3750 625 312 8/16 156 4/16 150 78 2/16 60 52 1/16 39 1/16 30 26 1/16 20 15 13 9 12/16 7 8/16 6 11/16 6 8/16 6 5 3 12/16 3 4/16 3 2 1 10/16 1 8/16 DLM PROGRAM VALUE (HEX) E 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DLL PROGRAM VALUE (HEX) A6 71 38 9C 96 4E 3C 34 27 1E 1A 14 F D 9 7 6 6 6 5 3 3 3 2 1 1 DLD PROGRAM VALUE (HEX)) 0 0 8 4 0 2 0 1 1 0 1 0 0 0 C 8 B 8 0 0 C 4 0 0 A 8 DATA ERROR RATE (%) 0 0 0 0 0 0 0 0.04 0 0 0.08 0 0 0.16 0.16 0 0.31 0.16 0 0 0 0.16 0 0 0.16 0
2.7
Transmitter
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 64 bytes of FIFO which includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X or 8X (if 8X sampling is selected via the 8XMODE Register) internal clock. A bit time is 16 (or 8) clock periods. The transmitter sends the start-bit followed by the number of data bits, inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are reported in the Line Status Register (LSR bit-5 and bit-6).
9
XR16V794
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE 2.7.1 Transmit Holding Register (THR) - Write Only
REV. 1.0.0
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits, parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input register to the transmit FIFO of 64 bytes when FIFO operation is enabled by FCR bit-0. Every time a write operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data location.
2.7.2 Transmitter Operation in non-FIFO Mode
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
FIGURE 5. TRANSMITTER OPERATION IN NON-FIFO MODE
Data Byte
Transmit Holding Register (THR)
THR Interrupt (ISR bit-1) Enabled by IER bit-1
16X or 8X Clock Transmit Shift Register (TSR)
M S B L S B
TXNOFIFO1
2.7.3
Transmitter Operation in FIFO Mode
The host may fill the transmit FIFO with up to 64 bytes of transmit data. The THR empty flag (LSR bit-5) is set whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the amount of data in the FIFO falls below its programmed trigger level. The transmit empty interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set when TSR/FIFO becomes empty.
FIGURE 6. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE
Transmit Data Byte
Transm it FIFO
THR Interrupt (ISR bit-1) falls below the programmed Trigger Level and then when becomes empty. FIFO is Enabled by FCR bit-0=1
Auto CTS Flow Control (CTS# pin) Flow Control Characters (Xoff1/2 and Xon1/2 Reg. Auto Software Flow Control
16X or 8X Clock
Transm it Data Shift Register (TSR)
T XF IF O 1
10
XR16V794
REV. 1.0.0
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
2.8
Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and 64 bytes of FIFO which includes a byte-wide Receive Holding Register (RHR). The RSR uses the 16X (or the 8X) clock for timing. It verifies and validates every bit on the incoming character in the middle of each data bit. On the falling edge of a start or false start bit, an internal receiver counter starts counting the number of 16X (or 8X) clocks. After 8 (or 4) clocks the start bit period should be at the center of the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this manner prevents the receiver from assembling a false character. The rest of the data bits and stop bits are sampled and validated in this same manner to prevent false framing. If there were any error(s), they are reported in the LSR register bits 2-4. Upon unloading the receive data byte from RHR, the receive FIFO pointer is bumped and the error tags are immediately updated to reflect the status of the data byte in RHR register. RHR can generate a receive data ready interrupt upon receiving a character or delay until it reaches the FIFO trigger level. Furthermore, data delivery to the host is guaranteed by a receive data ready time-out interrupt when data is not received for 4 word lengths as defined by LCR[1:0] plus 12 bits time. This is equivalent to 3.7-4.6 character times. The RHR interrupt is enabled by IER bit-0.
2.8.1 Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift Register. It provides the receive data interface to the host processor. The RHR register is part of the receive FIFO of 64 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data byte are immediately updated in the LSR bits 2-4.
FIGURE 7. RECEIVER OPERATION IN NON-FIFO MODE
16X or 8X Clock
Receive Data Shift Register (RSR)
Data Bit Validation
Receive Data Characters
Receive Data Byte and Errors
Error Tags in LSR bits 4:2
Receive Data Holding Register (RHR)
RHR Interrupt (ISR bit-2)
RXFIFO1
11
XR16V794
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE FIGURE 8. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE
REV. 1.0.0
16X or 8X Clock Receive Data Shift Register (RSR) Data Bit Validation
Example: 64 bytes by 11-bit wide FIFO Error Tags (64-sets)
Receive Data Characters
- RX FIFO trigger level selected at 16 bytes (See Note Below)
Data falls to 8
Receive Data FIFO
RTS# re-asserts when data falls below the flow control trigger level to restart remote transmitter. Enable by EFR bit-6=1, MCR bit-1. RHR Interrupt (ISR bit-2) programmed for desired FIFO trigger level. FIFO is Enabled by FCR bit-0=1 RTS# de-asserts when data fills above the flow control trigger level to suspend remote transmitter. Enable by EFR bit-6=1, MCR bit-1.
FIFO Trigger=16
Data fills to 24 Error Tags in LSR bits 4:2
Receive Data Byte and Errors
Receive Data
RXFIFO1
NOTE: Table-B selected as Trigger Table for Figure 8 (see Table 14).
2.9
THR and RHR Register Locations
The THR and RHR register addresses for channel 0 to channel 7 are shown in Table 5 below. The THR and RHR for channels 0 to 7 are located at address 0x00, 0x10, 0x20, 0x30, 0x40, 0x50, 0x60 and 0x70 respectively. Transmit data byte is loaded to the THR when writing to that address and receive data is unloaded from the RHR register when reading that address. Both THR and RHR registers are 16C550 compatible in 8-bit format, so each bus operation can only write or read in bytes..
TABLE 5: TRANSMIT AND RECEIVE HOLDING REGISTER LOCATIONS, 16C550 COMPATIBLE
THR and RHR Address Locations For CH0 to CH3 (16C550 Compatible) CH0 0x00 Write THR CH0 0x00 Read RHR CH1 0x10 Write THR CH1 0x10 Read RHR CH2 0x20 Write THR CH2 0x20 Read RHR CH3 0x30 Write THR CH3 0x30 Read RHR Bit-7 Bit-7 Bit-7 Bit-7 Bit-7 Bit-7 Bit-7 Bit-7 Bit-6 Bit-6 Bit-6 Bit-6 Bit-6 Bit-6 Bit-6 Bit-6 Bit-5 Bit-5 Bit-5 Bit-5 Bit-5 Bit-5 Bit-5 Bit-5 Bit-4 Bit-4 Bit-4 Bit-4 Bit-4 Bit-4 Bit-4 Bit-4 Bit-3 Bit-3 Bit-3 Bit-3 Bit-3 Bit-3 Bit-3 Bit-3 Bit-2 Bit-2 Bit-2 Bit-2 Bit-2 Bit-2 Bit-2 Bit-2 Bit-1 Bit-1 Bit-1 Bit-1 Bit-1 Bit-1 Bit-1 Bit-1 Bit-0 Bit-0 Bit-0 Bit-0 Bit-0 Bit-0 Bit-0 Bit-0
784THRRHR1
12
XR16V794
REV. 1.0.0
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
2.10
Auto RTS/DTR Hardware Flow Control Operation
Automatic RTS/DTR flow control is used to prevent data overrun to the local receiver FIFO. The RTS#/DTR# output pin is used to request remote unit to suspend/resume data transmission. The flow control features are individually selected to fit specific application requirement (see Figure 9):
* Select RTS (and CTS) or DTR (and DSR) through MCR bit-2. * Enable auto RTS/DTR flow control using EFR bit-6. * The auto RTS or auto DTR function must be started by asserting the RTS# or DTR# output pin (MCR bit-1 or
bit-0 to a logic 1, respectively) after it is enabled.
* If using programmable RX FIFO trigger levels, hysteresis levels can be selected via FCTR bits 3-0.
With the Auto RTS function enabled, the RTS# output pin will not be de-asserted (HIGH) when the receive FIFO reaches the programmed trigger level, but will be de-asserted when the FIFO reaches the next trigger level for Trigger Tables A-C (See Table 14). The RTS# output pin will be asserted (LOW) again after the FIFO is unloaded to the next trigger level below the programmed trigger level. For Trigger Table D (or programmable trigger levels), the RTS# output pin is de-asserted when the the RX FIFO level reaches the RX trigger level plus the hysteresis level and is asserted when the RX FIFO level falls below the RX trigger level minus the hysteresis level. However, even under these conditions, the 794 will continue to accept data until the receive FIFO is full if the remote UART transmitter continues to send data.
* If used, enable RTS/DTR interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt
when the RTS#/DTR# pin makes a transition: ISR bit-5 will be set to 1.
2.10.1 Auto CTS/DSR Flow Control
Automatic CTS/DSR flow control is used to prevent data overrun to the remote receiver FIFO. The CTS/DSR pin is monitored to suspend/restart local transmitter. The flow control features are individually selected to fit specific application requirement (see Figure 9):
* Select CTS (and RTS) or DSR (and DTR) through MCR bit-2. * Enable auto CTS/DSR flow control using EFR bit-7.
With the Auto CTS or Auto DTR function enabled, the UART will suspend transmission as soon as the stop bit of the character in the Transmit Shift Register has been shifted out. Transmission is resumed after the CTS#/ DTR# input is re-asserted (LOW), indicating more data may be sent.
* If used, enable CTS/DSR interrupt through IER bit-7 (after setting EFR bit-4). The UART issues an interrupt
when the CTS#/DSR# pin makes a transition: ISR bit-5 will be set to a logic 1, and UART will suspend TX transmissions as soon as the stop bit of the character in process is shifted out. Transmission is resumed after the CTS#/DSR# input returns LOW, indicating more data may be sent.
13
XR16V794
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE FIGURE 9. AUTO RTS/DTR AND CTS/DSR FLOW CONTROL OPERATION
Local UART UARTA Receiver FIFO Trigger Reached Auto RTS Trigger Level Transmitter Auto CTS Monitor RXA TXB Remote UART UARTB Transmitter Auto CTS Monitor Receiver FIFO Trigger Reached Auto RTS Trigger Level
REV. 1.0.0
RTSA# TXA
CTSB# RXB
CTSA# Assert RTS# to Begin Transmission 1 ON 2 7 ON 3 8 OFF
RTSB#
RTSA# CTSB# TXB
OFF
10 11
ON ON
Data Starts 4 RXA FIFO INTA (RXA FIFO Interrupt) Receive RX FIFO Data Trigger Level 5
6
Suspend
Restart 9
RTS High Threshold
RTS Low Threshold
12
RX FIFO Trigger Level
RTSCTS1
The local UART (UARTA) starts data transfer by asserting RTSA# (1). RTSA# is normally connected to CTSB# (2) of remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO (4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and continues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows (7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its transmit shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9), UARTA re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until next receive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB with RTSB# and CTSA# controlling the data flow.
2.11
Auto Xon/Xoff (Software) Flow Control
When software flow control is enabled (See Table 18), the 794 compares one or two sequential receive data characters with the programmed Xon-1,2 or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed Xoff-1,2 value(s), the 794 will halt transmission (TX) as soon as the current character has completed transmission. When a match occurs, the Xoff (if enabled via IER bit-5) flag will be set and the interrupt output pin will be activated. Following a suspension due to a match of the Xoff character(s), the 794 will monitor the receive data stream for a match to the Xon-1,2 character(s). If a match is found, the 794 will resume operation and clear the flags (ISR bit-4). Reset initially sets the contents of the Xon1, Xon2, Xoff1 and Xoff2 flow control registers to '0'. Following reset, any desired Xon/Xoff value can be used for software flow control. Different conditions can be set to detect Xon/ Xoff characters (See Table 18) and suspend/resume transmissions. When double 8-bit Xon/Xoff characters are selected, the 794 compares two consecutive receive characters with two software flow control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above described flow control mechanisms, flow control characters are not placed (stacked) in the user accessible RX data buffer or FIFO.
14
XR16V794
REV. 1.0.0
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
In the event that the receive buffer is overfilling and flow control needs to be executed, the 794 automatically sends an Xoff message (when enabled) via the serial TX output to the remote modem. The 794 sends the Xoff1,2 characters two character times (= time taken to send two characters at the programmed baud rate) after the receive FIFO crosses the programmed trigger level (for all trigger tables A-D). To clear this condition, the 794 will transmit the programmed Xon-1,2 characters as soon as receive FIFO is less than one trigger level below the programmed trigger level (for Trigger Tables A, B, and C) or when receive FIFO is less than the trigger level minus the hysteresis value (for Trigger Table D). This hysteresis value is the same as the Auto RTS/DTR Hysteresis value in Table 17. Table 6 below explains this when Trigger Table-B (See Table 14) is selected.
TABLE 6: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL
RX TRIGGER LEVEL 8 16 24 28 INT PIN ACTIVATION 8 16 24 28 XOFF CHARACTER(S) SENT (CHARACTERS IN RX FIFO) 8* 16* 24* 28* XON CHARACTER(S) SENT (CHARACTERS IN RX FIFO) 0 8 16 24
* After the trigger level is reached, an xoff character is sent after a short span of time (= time required to send 2 characters); for example, after 2.083ms has elapsed for 9600 baud and 10-bit word length setting.
2.12
Special Character Detect
A special character detect feature is provided to detect an 8-bit character when bit-5 is set in the Enhanced Feature Register (EFR). When this character (Xoff2) is detected, it will be placed in the FIFO along with normal incoming RX data. The 794 compares each incoming receive character with Xoff-2 data. If a match exists, the received data will be transferred to FIFO and ISR bit-4 will be set to indicate detection of special character. Although the Internal Register Table shows Xon, Xoff Registers with 8 bits of character information, the actual number of bits is dependent on the programmed word length. Line Control Register (LCR) bits 0-1 defines the number of character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. The word length selected by LCR bits 0-1 also determines the number of bits that will be used for the special character comparison. Bit-0 in the Xon, Xoff Registers corresponds to the LSB bit for the receive character.
2.13 Auto RS485 Half-duplex Control
The auto RS485 half-duplex direction control changes the behavior of the transmitter when enabled by FCTR bit-5. It asserts RTS# or DTR# (LOW) after a specified delay indicated in MSR[7:4] following the last stop bit of the last character that has been transmitted. This helps in turning around the transceiver to receive the remote station's response. The delay optimizes the time needed for the last transmission to reach the farthest station on a long cable network before switching off the line driver. This delay prevents undesirable line signal disturbance that causes signal degradation. When the host is ready to transmit next polling data packet again, it only has to load data bytes to the transmit FIFO. The transmitter automatically de-asserts RTS# or DTR# output (HIGH) prior to sending the data. The auto RS485 half-duplex direction control also changes the transmitter empty interrupt to TSR empty instead of THR empty.
2.14 Infrared Mode
Each UART in the 794 includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association) version 1.0. The input pin ENIR conveniently activates all 4 UART channels to start up in the infrared mode. Note that the ENIR pin is sampled when the RST# input is de-asserted. This global control pin enables the MCR bit-6 function in every UART channel register. After power up or a reset, the software can overwrite MCR bit-6 if so desired. ENIR and MCR bit-6 also disable the receiver while the transmitter is sending data. This prevents echoed data from reaching the receiver. The global activation ENIR pin prevents the infrared emitter from turning on and drawing large amount of current while the system is starting up. When the infrared feature is enabled, the transmit data outputs, TX[7:0], would idle at logic zero level. Likewise, the RX [7:0] inputs assume an idle level of logic zero.
15
XR16V794
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
REV. 1.0.0
The infrared encoder sends out a 3/16 of a bit wide HIGH-pulse for each "0" bit in the transmit data stream. This signal encoding reduces the on-time of the infrared LED, hence reduces the power consumption. See Figure 10 below. The infrared decoder receives the input pulse from the infrared sensing diode on RX pin. Each time it senses a light pulse, it returns a logic zero to the data bit stream. The decoder also accepts (when FCTR bit-4 = 1) an inverted IR-encoded input signal. This option supports active LOW instead of normal active HIGH pulse from some infrared modules on the market.
FIGURE 10. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING
Character Start Data Bits 1 0 1 0 0 1 1 0 Stop 1 1/2 Bit Time 3/16 Bit Time
IrEncoder-1
TX Data
0
Transmit IR Pulse (TX Pin) Bit Time
Receive IR Pulse (RX pin)
Bit Time 1/16 Clock Delay
RX Data
0 Start
1
0
1
0
0
11
0
1 Stop
IRdecoder-
Data Bits Character
16
XR16V794
REV. 1.0.0
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE Sleep Mode with Auto Wake-Up
2.15
The 794 supports low voltage system designs, hence, a sleep mode is included to reduce its power consumption when the chip is not actively used. All of these conditions must be satisfied for the 794 to enter sleep mode:

no interrupts pending for all 4 channels of the 794 (ISR bit-0 = 1) SLEEP register = 0xFF modem inputs are not toggling (MSR bits 0-3 = 0) RX input pin of all 4 channels are idling HIGH
The 794 stops its crystal oscillator to conserve power in the sleep mode. User can check the XTAL2 pin for no clock output as an indication that the device has entered the sleep mode. The 794 resumes normal operation by any of the following:

a receive data start bit transition (HIGH to LOW) a data byte is loaded to the transmitter, THR or FIFO a change of logic state on any of the modem or general purpose serial inputs: CTS#, DSR#, CD#, RI#
If the 794 is awakened by any one of the above conditions, it will generate an interrupt. If the interrupt for the event that woke up the 794 is not enabled, then a special wake-up interrupt occurs where reading the interrupt status register will return a "no interrupt" indication. For example, there is a change of state on the CTS# input that wakes up the 794, but the MSR interrupt is not enabled. Reading the interrupt status register will return a value indicating that there are no pending interrupts and will clear the wake-up interrupt. The 794 will return to the sleep mode automatically after all interrupting conditions have been serviced and cleared. If the 794 is awakened by the modem inputs, a read to the MSR is required to reset the modem inputs. In any case, the sleep mode will not be entered while an interrupt is pending in any channel. The 794 will stay in the sleep mode of operation until it is disabled by setting SLEEP = 0x00. A word of caution: owing to the starting up delay of the crystal oscillator after waking up from sleep mode, the first few receive characters may be lost. The number of characters lost during the restart also depends on your operating data rate. More characters are lost when operating at higher data rate.
17
XR16V794
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE 2.16 Internal Loopback
REV. 1.0.0
Each UART channel provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally. Figure 11 shows how the modem port signals are re-configured. Transmit data from the transmit shift register output is internally routed to the receive shift register input allowing the system to receive the same data that it was sending. The TX pin is held at HIGH or mark condition while RTS# and DTR# are de-asserted (HIGH), and CTS#, DSR# CD# and RI# inputs are ignored.
FIGURE 11. INTERNAL LOOP BACK
VCC Transmit Shift Register (THR/FIFO) MCR bit-4=1 Internal Data Bus Lines and Control Signals Receive Shift Register (RHR/FIFO) VCC RTS# [3:0] Modem / General Purpose Control Logic RTS# TX [3:0]
RX [3:0]
CTS# VCC DTR#
CTS# [3:0] DTR# [3:0]
DSR# OP1# RI# OP2# CD#
DSR# [3:0]
RI# [3:0] CD# [3:0]
3.0
XR16V794 REGISTERS
The XR16V794 octal UART register set consists of the Device Configuration Registers that are accessible directly from the data bus for programming general operating conditions of the UARTs and monitoring the status of various functions. These functions include all 4 channel UART's interrupt control and status, 16-bit general purpose timer control and status, sleep mode, soft-reset, and device identification and revision. Also, each UART channel has its own set of internal UART Configuration Registers for its own operation control, status reporting and data transfer. These registers are mapped into a 256-byte of the data memory address space. The following paragraphs describe all the registers in detail.
18
XR16V794
REV. 1.0.0
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
FIGURE 12. THE XR16V794 REGISTERS
0x00-0F Channel 0 0x10-1F Channel 1 Channel 2 8-bit Data Bus Interface Channel 3 0x40-7F (reserved) INT0, INT1, INT2, INT3, TIMER, SLEEP, RESET 0x80-8F Device Configuration Registers 4 channel Interrupts, 16-bit Timer/Counter, Sleep, Reset, DVID, DREV
784REGS
0x20-2F 0x30-3F
UART[3:0] Configuration Registers 16550 Compatible and Exar Enhanced Registers
3.1
DEVICE CONFIGURATION REGISTER SET
The device configuration registers are directly accessible from the bus. This provides easy programming of general operating parameters to the 794 UART and for monitoring the status of various functions. The device configuration registers are mapped onto address 0x80-8F as shown on the register map in Table 8 and Figure 12. These registers provide global controls and status of all 4 channel UARTs that include interrupt status, 16-bit general purpose timer control and status, 8X or 16X sampling clock, sleep mode control, softreset control, simultaneous UART initialization, and device identification and revision.
TABLE 7: XR16V794 REGISTER SETS
ADDRESS [A7:A0] 0x00 - 0x0F 0x10 - 0x1F 0x20 - 0x2F 0x30 - 0x3F 0x40 - 0x7F 0x80 - 0x8F UART CHANNEL SPACE UART channel 0 Registers UART channel 1 Registers UART channel 2 Registers UART channel 3 Registers None Device Configuration Registers (Table 8) REFERENCE (Table 11 & 12) (Table 11 & 12) (Table 11 & 12) (Table 11 & 12) First 8 registers are 16550 compatible Reserved Interrupt registers and global controls COMMENT
19
XR16V794
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
REV. 1.0.0
TABLE 8: DEVICE CONFIGURATION REGISTERS
ADDRESS READ/ [A7:A0] WRITE 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B R R R R R/W R R/W REGISTER Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 UART 3 source bit 0 UART 3 bit 2 Bit 2 UART 2 UART 0 bit 2 interrupt bit 1 Bit 1 UART 1 interrupt bit 1 source bit 0 Bit 0 UART 0 source bit 0 UART 2 bit 2
INT Source Reserved Reserved Reserved Reserved INT 1 INT 2 INT 3 TIMER CTRL TIMER TIMER LSB UART 2 bit 1 source bit 0 UART 1 bit 2 interrupt bit 1
Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0 0 bit 7 bit 7 UART 7 0 0 0 bit 6 bit 6 UART 6 0 0 0 bit 5 bit 5 UART 5 0 0 0 bit 4 bit 4 UART 4 0 clock source 0 bit 3 bit 3 UART 3 0 Reset UART 3 Enable sleep UART 3 bit 3 0 0 function select 0 bit 2 bit 2 UART 2 0 Reset UART 2 Enable sleep UART 2 bit 2 1 0 start timer 0 bit 1 bit 1 UART 1 0 Reset UART 1 Enable sleep UART 1 bit 1 0 0 enable timer INT 0 bit 0 bit 0 UART 0 0 Reset UART 0 Enable sleep UART 0 bit 0 0 write to all UARTs
R/W TIMER MSB R/W R W R/W 8X MODE REGA RESET SLEEP
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
0x8C 0x8D 0x8E
R R R/W
DREV DVID REGB
bit 7 0 0
bit 6 1 0
bit 5 0 0
bit 4 0 0
3.1.1
The Global Interrupt Source Registers
The XR16V794 has a global interrupt source register set that consists of 4 consecutive registers [INT0, INT1, INT2 and INT3]. The four registers are in the device configuration register address space.
INT3 [0x00] INT2 [0x00] INT1 [0x00] INT0 [0x00]
All four registers default to logic zero (as indicated in square braces) for no interrupt pending. All 4 channel interrupts are enabled or disabled in each channel's IER register. INT0 shows individual status for each channel while INT1, INT2 and INT3 show the details of the source of each channel's interrupt with its unique 3bit encoding. Figure 13 shows the 4 interrupt registers in sequence for clarity. The 16-bit timer and sleep wake-up interrupts are masked in the device configuration registers, TIMERCNTL and SLEEP. An interrupt is generated (if enabled) by the 794 when awakened from sleep if all 4 channels were placed in the sleep mode previously. Each bit gives an indication of the channel that has requested for service. For example, bit-0 represents channel 0 and bit-3 indicates channel 3. Logic one indicates the channel N [3:0] has called for service. Bits 4 to 7 are reserved and remains at logic zero. The interrupt bit clears after reading the appropriate register of the interrupting UART channel register (ISR, LSR and MSR). SEE "INTERRUPT CLEARING:" ON PAGE 30. for interrupt clearing details.
20
XR16V794
REV. 1.0.0
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE INT0 Channel Interrupt Indicator:
3.1.1.1
INT0 Register Individual UART Channel Interrupt Status Bit-7 Rsvd Bit-6 Rsvd Bit-5 Rsvd Bit-4 Rsvd Bit-3 Ch-3 Bit-2 Ch-2 Bit-1 Ch-1 Bit-0 Ch-0
3.1.1.2
INT1, INT2 and INT3 Interrupt Source Locator
INT3, INT2 and INT1 provide a 24-bit (3 bits per channel) encoded interrupt indicator. Table 9 shows the 3 bit encoding and their priority order. The 16-bit Timer time-out interrupt will show up only as a channel 0 interrupt. For other channels, interrupt 7 is reserved.
.
FIGURE 13. THE GLOBAL INTERRUPT REGISTERS, INT0, INT1, INT2 AND INT3
Interrupt Registers, INT0, INT1, INT2 and INT3
INT3 Register Reserved Bit 2 Bit 1 Bit 0 Bit 2 Reserved Bit 1 Bit 0 Bit 2 Reserved Bit 1 Bit 0 Bit 2 INT2 Register Reserved Bit 1 Bit 0 Bit 2 Channel-3 Bit 1 Bit 0 Bit 2 Channel-2 Bit 1 Bit 0 Bit 2 INT1 Register Channel-1 Bit 1 Bit 0 Bit 2 Channel-0 Bit 1 Bit 0
INT0 Register Rsvd Rsvd Rsvd Rsvd Bit-7 Bit-6 Bit-5 Bit-4 Ch-3 Ch-2 Bit-3 Ch-1 Ch-0 Bit-0
Bit-2 Bit-1
TABLE 9: UART CHANNEL [7:0] INTERRUPT SOURCE ENCODING AND CLEARING
PRIORITY x 1 2 3 4 Bit Bit Bit 2 1 0 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 None (or wake-up indicator) RXRDY & RX Line Status (logic OR of LSR[4:1]). RXRDY INT clears by reading data in the RX FIFO until it falls below the trigger level; RX Line Status INT cleared after reading LSR register. RXRDY Time-out: Cleared same way as RXRDY INT. TXRDY, THR or TSR (auto RS485 mode) empty, clears after reading ISR register. MSR, RTS/CTS or DTR/DSR delta or Xoff/Xon or special character detected. The first two clears after reading MSR register; Xoff/Xon or special char. detect INT clears after reading ISR register. Reserved. Reserved. TIMER Time-out, shows up as a channel 0 INT. It clears after reading the TIMERCNTL register. Reserved in other channels. INTERRUPT SOURCE(S) AND CLEARING
5 6 7
1 1 1
0 1 1
1 0 1
21
XR16V794
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE 3.1.2
REV. 1.0.0
General Purpose 16-bit Timer/Counter [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (DEFAULT 0XXX-XX-00-00)
The 794 includes a 16-bit general purpose timer/counter. Its clock source may be selected from internal crystal oscillator or externally on pin TMRCK. The timer can be set to be a single-shot for a one-time event or retriggerable for a periodic signal. An interrupt may be generated when the timer times out and will show up as a Channel 0 interrupt (see Table 9). It is controlled through 4 configuration registers [TIMERCNTL, TIMER, TIMELSB, TIMERMSB]. These registers provide start/stop and re-triggerable or one-shot operation (see Table 10 below). The time-out output of the Timer can be set to generate an interrupt for system or event alarm.
3.1.2.1 TIMERMSB [7:0] and TIMERLSB [7:0]
TIMERMSB and TIMERLSB form a 16-bit value. The least-significant bit of the timer is being bit-0 of the TIMERLSB with most-significant-bit being bit-7 in TIMERMSB. Notice that these registers do not hold the current counter value when read. Default value is zero (timer disabled) upon powerup and reset.
16-Bit Timer/Counter Programmable Registers
TIMERMSB Register Bit-15 Bit-14 Bit-13 Bit-12 Bit-11 Bit-10 Bit-9 Bit-8 Bit-7 Bit-6 TIMERLSB Register Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
3.1.2.2 3.1.2.3
TIMER [7:0] Reserved TIMERCNTL [7:0] Register
The bits 3:0 of this register are used to issue commands. The commands are self-clearing, so reading this register does not show the last written command. Reading this register returns a value of 0x01 when there is a Timer interrupt pending and 0x00 at all other times.
TABLE 10: TIMER CONTROL COMMANDS
TIMERCNTL [7:4] TIMERCNTL [3:0] Reserved These bits are used to invoke a series of commands that control the function of the Timer/Counter. The commands 1011 to 1111 are reserved. 0001: Enable Timer Interrupt 0010: Disable Timer Interrupt 0011: Select One-shot mode 0100: Select Re-triggerable mode 0101: Select Internal Crystal Oscillator output as clock source for the Timer 0110: Select External Clock source (through TMRCK pin) for the Timer 0111: Reserved 1000: Reserved 1001: Start Timer 1010: Stop Timer 1011: Reset Timer
22
XR16V794
REV. 1.0.0
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
TIMER OPERATION
The following paragraphs describe the operation of the 16-bit Timer/Counter. The following conventions will be used in this discussion:

'N' is the 16-bit value programmed in the TIMER MSB, LSB registers `N' can take any value from 0x0002 to 0xFFFF.
Timer Interrupt
In the one-shot mode, the Timer will issue an interrupt 'N' clocks after the Timer is started. This is the time when the Timer times-out in the one-shot mode. In the re-triggerable mode, the Timer will keep issuing an interrupt every 'N' clocks. This is shown in Figure 15, where the time between successive time-outs (in retriggereble mode) is 'N' clocks. The Timer interrupt can be cleared by reading the TIMERCNTL register. The TIMERCNTL will read a value of 0x01 when there is an interrupt and a 0x00 at all other times.
FIGURE 14. TIMER/COUNTER CIRCUIT.
TIMERMSB and TIMERLSB (16-bit Value)
Timer Interrupt TMRCK OSC. CLOCK 1 0
16-Bit Timer/Counter
1 0
Timer Interrupt No Interrupt
Clock Select Start/Stop
TIMERCNTL COMMANDS Single shot/Re-triggerable
Timer Interrupt Enable/ Disable
FIGURE 15. INTERRUPT OUTPUT IN ONE-SHOT AND RE-TRIGGERABLE MODES
Timer Started Timer Timed Out TIMERCNTL read
One-shot Mode
Timer Timed TIMERCNTL Out read
Timer Timed Out
Re-triggerable Mode
23
XR16V794
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE 3.1.3 8XMODE [7:0] (default 0x00)
REV. 1.0.0
Each bit selects 8X or 16X sampling rate for that UART channel, bit-0 is channel 0. Logic 0 (default) selects normal 16X sampling with logic one selects 8X sampling rate. Transmit and receive data rates will double by selecting 8X.
8XMODE Register Individual UART Channel 8X Clock Mode Enable Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 Ch-7 Ch-6 Ch-5 Ch-4 Ch-3 Ch-2 Ch-1 Ch-0
3.1.4
REGA [7:0](default 0x00) RESET [7:0] (default 0x00)
RESET Register Individual UART Channel Reset Enable Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 Ch-7 Ch-6 Ch-5 Ch-4 Ch-3 Ch-2 Ch-1 Ch-0
Reserved.
3.1.5
The 8-bit RESET register provides the software with the ability to reset the UART(s) when there is a need. Each bit is self-resetting after it is written a logic 1 to perform a reset to that channel. All registers in that channel will be reset to the default condition, see Table 19 for details. As an example, bit-0 =1 resets UART channel 0 with bit-7=1 resets channel 7.
3.1.6 SLEEP [7:0] (default 0x00)
The 8-bit Sleep register enables each UART separately to enter Sleep mode. Sleep mode reduces power consumption when the system needs to put the UART(s) to idle. The UART enters sleep mode when there is no interrupt pending. When all 4 UARTs are put to sleep, the on-chip oscillator shuts off to further conserve power. In this case, the octal UART is awaken by any of the UART channel on from a receive data byte or a change on the serial port. The UART is ready after 32 crystal clocks to ensure full functionality. Also, a special interrupt is generated with an indication of no pending interrupt. Logic 0 (default) and logic 1 disable and enable sleep mode respectively.
SLEEP Register Individual UART Channel Sleep Enable Ch-7 Ch-6 Ch-5 Ch-4 Ch-3 Ch-2 Ch-1 Ch-0 Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
3.1.7
Device Identification and Revision
There are 2 internal registers that provide device identification and revision, DVID and DREV registers. The 8bit content in the DVID register provides device identification. A return value of 0x44 from this register indicates the device is a XR16V794. The DREV register returns a 8-bit value of 0x01 for revision A, 0x02 for revision B and so on. This information is very useful to the software driver for identifying which device it is communicating with and to keep up with revision changes.
24
XR16V794
REV. 1.0.0
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE DVID [7:0] (default 0x48)
3.1.7.1
Device identification for the type of UART. The Device ID for the V794 is 0x44. Examples: XR16V794 = 0x44 XR16L784 = 0x24
3.1.7.2 3.1.8 DREV [7:0] (default (0x01) REGB [7:0] (default 0x00)
Revision number of the XR16V794. A 0x01 represents "revision-A" with 0x02 for rev-B and so forth.
REGB[0]: Simultaneous write to all 4 UARTs
* Logic 0 = Write to each UART configuration register individually (default). * Logic 1 = Enable simultaneous write to all 4 UART configuration registers. This can be very useful during
device initialization in the power-up and reset routines.
REGB[7:1]
Reserved.
25
XR16V794
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE 3.2 UART CHANNEL CONFIGURATION REGISTERS
REV. 1.0.0
The first 8 registers are 16550 compatible with EXAR enhanced feature registers located on the upper 8 addresses. The 4 sets of UART configuration registers are decoded using address lines A0 to A3 as shown below.
TABLE 11: UART CHANNEL CONFIGURATION REGISTERS.
ADDRESS A3 A2 A1 A0 16550 COMPATIBLE 0 0 00 RHR - Receive Holding Reg THR - Transmit Holding Register DLL - Divisor LSB DLM - Divisor MSB DLD - Divisor Fractional Part IER - Interrupt Enable Reg ISR - Interrupt Status Reg FCR - FIFO Control Reg LCR - Line Control Reg MCR - Modem Control Reg LSR - Line Status Reg reserved MSR - Modem Status Reg - Auto RS485 Delay SPR - Scratch Pad Reg ENHANCED REGISTER 1 1 1 0 0 0 00 01 10 FCTR EFR - Enhanced Function Reg TXCNT - Transmit FIFO Level Counter TXTRG - Transmit FIFO Trigger Level RXCNT - Receive FIFO Level Counter RXTRG - Receive FIFO Trigger Level Xoff-1 - Xoff Character 1 Xchar Xoff-2 - Xoff Character 2 reserved Xon-1 - Xon Character 1 reserved Xon-2 - Xon Character 2 reserved Read/Write Read/Write Read-only Write-only Read-only Write-only Write-only Read-only Write-only Read-only Write-only Read-only Write-only Read-only Xon,Xoff Rcvd. Flags Read-only Write-only Read/Write Read/Write Read/Write Read/Write Read-only Write-only Read/Write Read/Write Read-only Write-only Read-only Write-only Read/Write LCR[7] = 0 REGISTER READ/WRITE COMMENTS
0 0 0 0 0
0 0 0 0 0
00 01 10 01 10
LCR[7] = 1 LCR[7] = 1 LCR[7] = 1 LCR[7] = 0 LCR[7] = 0
0 0 0
0 1 1
11 00 01
0
1
10
0
1
11
1
0
11
1
1
00
1
1
01
1
1
10
1
1
11
26
XR16V794
REV. 1.0.0
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
TABLE 12: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED BY EFR BIT-4.
ADDRESS A3-A0 0000 0000 0000 0001 0010 0001 REG NAME RHR THR DLL DLM DLD IER READ/ WRITE R W R/W R/W R/W R/W BIT-7 Bit-7 Bit-7 Bit-7 Bit-7 0 0/ BIT-6 Bit-6 Bit-6 Bit-6 Bit-6 0 0/ BIT-5 Bit-5 Bit-5 Bit-5 Bit-5 0 0/ BIT-4 Bit-4 Bit-4 Bit-4 Bit-4 0 0 BIT-3 Bit-3 Bit-3 Bit-3 Bit-3 Bit-3 BIT-2 Bit-2 Bit-2 Bit-2 Bit-2 Bit-2 BIT-1 Bit-1 Bit-1 Bit-1 Bit-1 Bit-1 BIT-0 Bit-0 Bit-0 Bit-0 Bit-0 Bit-0 RX Data Int. Enable COMMENT LCR[7]=0 LCR[7]=0 LCR[7]=1 LCR[7]=1 LCR[7]=1
CTS/ RTS/ Xon/Xoff/ DSR# Int. DTR# Int. Sp. Char. Enable Enable Int. Enable 0010 ISR R FIFOs Enable FIFOs Enable 0/ 0/
Modem RX Line TX Ready Status Int. Status Int. Int. Enable Enable Enable
LCR[7]=0
DeltaXoff/special char Flow Cntl 0010 FCR W RX FIFO Trigger RX FIFO Trigger 0/ TX FIFO Trigger 0011 LCR R/W Divisor Enable Set TX Break 0/ TX FIFO Trigger
INT Source Bit-3 DMA Mode
INT Source Bit-2 TX FIFO Reset
INT Source Bit-1 RX FIFO Reset
INT Source Bit-0 FIFOs Enable
LCR[7]=0
LCR[7]=0
Set Parity Even Parity
Parity Enable
Stop Bits
Word Length Bit-1
Word Length Bit-0
0100
MCR
R/W
0/ BRG Prescaler
0/ IR Enable
0/ XonAny
Internal Loopback Enable
(OP2)1 TX char Immediate
(OP1)1 RTS/DTR Flow Sel
RTS# Pin DTR# Pin Control Control
0101
LSR
R/W
RX FIFO TransmitERROR ter Empty CD RI
TX FIFO Empty DSR
RX Break
RX Fram- RX Parity RX OverError ing Error run Delta CD# Disable TX Bit-3 Delta RI# Disable RX Bit-2 Bit-1 Delta DSR#
RX Data Ready Delta CTS#
0110
MSR
R
CTS
MSR
W
RS485 DLY-3 Bit-7 TRG Table Bit-1
RS485 DLY-2 Bit-6 TRG Table Bit-0
RS485 DLY-1 Bit-5 Auto RS485 Enable Special Char Select
RS485 DLY-0 Bit-4 Invert IR RX Input
0111 1000
SPR FCTR
R/W R/W
Bit-0
User Data
RTS/DTR RTS/DTR RTS/DTR RTS/DTR Hyst Bit-3 Hyst Bit-2 Hyst Bit-1 Hyst Bit-0
1001
EFR
R/W
Auto Auto CTS/DSR RTS/DTR Enable Enable
Enable IER [7:5], ISR [5:4], FCR[5:4], MCR[7:5, 3:2] MSR[7:2]
Software Software Software Software Flow Cntl Flow Cntl Flow Cntl Flow Cntl Bit-3 Bit-2 Bit-1 Bit-0
1010
TXCNT
R
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
27
XR16V794
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
REV. 1.0.0
TABLE 12: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED BY EFR BIT-4.
ADDRESS A3-A0 1010 1011 1011 1100 REG NAME TXTRG RXCNT RXTRG XCHAR READ/ WRITE W R W R BIT-7 Bit-7 Bit-7 Bit-7 0 BIT-6 Bit-6 Bit-6 Bit-6 0 BIT-5 Bit-5 Bit-5 Bit-5 0 BIT-4 Bit-4 Bit-4 Bit-4 0 BIT-3 Bit-3 Bit-3 Bit-3 TX Xon Indicator Bit-3 Bit-3 Bit-3 Bit-3 BIT-2 Bit-2 Bit-2 Bit-2 TX Xoff Indicator Bit-2 Bit-2 Bit-2 Bit-2 BIT-1 Bit-1 Bit-1 Bit-1 Xon Det. Indicator Bit-1 Bit-1 Bit-1 Bit-1 BIT-0 Bit-0 Bit-0 Bit-0 Xoff Det. Indicator Bit-0 Bit-0 Bit-0 Bit-0 Self clear after read COMMENT
1100 1101 1110 1111
XOFF1 XOFF2 XON1 XON2
W W W W
Bit-7 Bit-7 Bit-7 Bit-7
Bit-6 Bit-6 Bit-6 Bit-6
Bit-5 Bit-5 Bit-5 Bit-5
Bit-4 Bit-4 Bit-4 Bit-4
NOTE: MCR bits 2 and 3 (OP1 and OP2 outputs) are not available in the XR16V794. They are present for 16C550 compatibility during Internal loopback, see Figure 11.
4.0 INTERNAL REGISTER DESCRIPTIONS 4.1 4.2 4.3 Receive Holding Register (RHR) - Read Only Transmit Holding Register (THR) - Write Only Interrupt Enable Register (IER) - Read/Write SEE "RECEIVER" ON PAGE 11.. SEE "TRANSMITTER" ON PAGE 9..
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR) and also encoded in INT (INT0-INT3) register in the Device Configuration Registers.
4.3.1 IER versus Receive FIFO Interrupt Mode Operation
When the receive FIFO (FCR BIT-0 = a logic 1) and receive interrupts (IER BIT-0 = logic 1) are enabled, the RHR interrupts (see ISR bits 3 and 4) status will reflect the following:
A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed trigger level. It will be cleared when the FIFO drops below the programmed trigger level. B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register status bit and the interrupt will be cleared when the FIFO drops below the trigger level. C. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to the receive FIFO. It is reset when the FIFO is empty. 4.3.2 IER versus Receive/Transmit FIFO Polled Mode Operation
When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 3:0 enables the XR16V794 in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either can be used in the polled mode by selecting respective transmit or receive control bit(s).
A. LSR BIT-0 indicates there is data in RHR (non-FIFO mode) or RX FIFO (FIFO mode). B. LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO may not be valid. C. LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any. D. LSR BIT-5 indicates THR (non-FIFO mode) or TX FIFO (FIFO mode) is empty. E. LSR BIT-6 indicates when both the transmit FIFO and TSR are empty. F. LSR BIT-7 indicates a data error in at least one character in the RX FIFO.
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XR16V794
REV. 1.0.0
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
IER[7]: CTS# Input Interrupt Enable (requires EFR bit-4=1)
* Logic 0 = Disable the CTS# interrupt (default). * Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition from
LOW to HIGH.
IER[6]: RTS# Output Interrupt Enable (requires EFR bit-4=1)
* Logic 0 = Disable the RTS# interrupt (default). * Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when RTS# pin makes a transition from
LOW to HIGH.
IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1)
* Logic 0 = Disable the software flow control, receive Xoff interrupt (default). * Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for
details.
IER[4]: Reserved. IER[3]: Modem Status Interrupt Enable
The Modem Status Register interrupt is issued whenever any of the delta bits of the MSR register (bits 3:0) is set.
* Logic 0 = Disable the modem status register interrupt (default). * Logic 1 = Enable the modem status register interrupt.
IER[2]: Receive Line Status Interrupt Enable
An Overrun error, Framing error, Parity error or detection of a Break character will result in an LSR interrupt. The 794 will issue an LSR interrupt immediately after receiving a character with an error. It will again re-issue the interrupt (if the first one has been cleared by reading the LSR register) when the character with the error is on the top of the FIFO, meaning the next one to be read out of the FIFO. For example, let's consider an incoming data stream of 0x55, 0xAA, etc and that the character 0xAA has a Parity error associated with it. Let's assume that the character 0x55 has not been read out of the FIFO yet. The 794 will issue an interrupt as soon as the stop bit of the character 0xAA is received. The LSR register will have only the FIFO error bit (bit-7) set and none of the other error bits (Bits 1,2,3 and 4) will be set, since the byte on the top of the FIFO is 0x55 which does not have any errors associated with it. When this byte has been read out, the 794 will issue another LSR interrupt and this time the LSR register will show the Parity bit (bit-2) set.
* Logic 0 = Disable the receiver line status interrupt (default). * Logic 1 = Enable the receiver line status interrupt.
IER[1]: TX Ready Interrupt Enable
In non-FIFO mode, a TX interrupt is issued whenever the THR is empty. In the FIFO mode, an interrupt is issued twice: once when the number of bytes in the TX FIFO falls below the programmed trigger level and again when the TX FIFO becomes empty. When autoRS485 mode is enabled (FCTR bit-5 = 1), the second interrupt is delayed until the transmitter (both the TX FIFO and the TX Shift Register) is empty.
* Logic 0 = Disable Transmit Ready Interrupt (default). * Logic 1 = Enable Transmit Ready Interrupt.
IER[0]: RX Interrupt Enable
The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when the receive FIFO has reached the programmed trigger level in the FIFO mode.
* Logic 0 = Disable the receive data ready interrupt (default). * Logic 1 = Enable the receiver data ready interrupt.
29
XR16V794
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE 4.4 Interrupt Status Register (ISR) - Read Only
REV. 1.0.0
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will give the user the current highest pending interrupt level to be serviced, others queue up for next service. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt Source Table, Table 13, shows the data values (bit 0-5) for the six prioritized interrupt levels and the interrupt sources associated with each of these interrupt levels.
4.4.1 Interrupt Generation:
* LSR is by any of the LSR bits 1, 2, 3 and 4. See IER bit-2 description above. * RXRDY is by RX trigger level. * RXRDY Time-out is by a 4-char plus 12 bits delay timer. * TXRDY is by TX trigger level or TX FIFO empty (or transmitter empty in auto RS-485 control). * MSR is by any of the MSR bits 0, 1, 2 and 3. * Receive Xoff/Special character is by detection of a Xoff or Special character. * CTS#/DSR# is when its transmitter toggles the input pin (from LOW to HIGH) during auto CTS/DSR flow
control enabled by EFR bit-7 and selection on MCR bit-2.
* RTS#/DTR# is when its receiver toggles the output pin (from LOW to HIGH) during auto RTS/DTR flow
control enabled by EFR bit-6 and selection on MCR bit-2.
* Wake-up Indicator is when the UART wakes up from the sleep mode.
4.4.2 Interrupt Clearing:
* LSR interrupt is cleared by a read to the LSR register. * RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level. * RXRDY Time-out interrupt is cleared by reading RHR. * TXRDY interrupt is cleared by a read to the ISR register or writing to THR. * MSR interrupt is cleared by a read to the MSR register. * Xoff interrupt is cleared by a read to ISR or when Xon character(s) is received. * Special character interrupt is cleared by a read to ISR or after the next character is received. * RTS#/DTR# and CTS#/DSR# status change interrupts are cleared by a read to the MSR register. * Wake-up Indicator is cleared by a read to the INT0 register.
]
TABLE 13: INTERRUPT SOURCE AND PRIORITY LEVEL
PRIORITY LEVEL 1 2 3 4 5 6 7 X BIT-5 0 0 0 0 0 0 1 0 ISR REGISTER STATUS BITS BIT-4 0 0 0 0 0 1 0 0 BIT-3 0 0 1 0 0 0 0 0 BIT-2 1 1 1 0 0 0 0 0 BIT-1 1 0 0 1 0 0 0 0 BIT-0 0 0 0 0 0 0 0 1 LSR (Receiver Line Status Register) RXRDY (Received Data Ready) RXRDY (Receive Data Time-out) TXRDY (Transmitter Holding Register Empty) MSR (Modem Status Register) RXRDY (Received Xon/Xoff or Special character) CTS#/DSR#, RTS#/DTR# change of state None (default) SOURCE OF THE INTERRUPT
30
XR16V794
REV. 1.0.0
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are enabled.
ISR[5:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Table 13). See "Section 4.4.1, Interrupt Generation:" on page 30 and "Section 4.4.2, Interrupt Clearing:" on page 30 for details.
ISR[0]: Interrupt Status
* Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
* Logic 1 = No interrupt pending. (default condition)
4.5 FIFO Control Register (FCR) - Write Only
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and select the DMA mode. The DMA, and FIFO modes are defined as follows:
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1) The FCTR Bits 5-4 are associated with these 2 bits. These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when the number of the characters in the FIFO crosses the trigger level. Table 14 shows the complete selections. Note that the receiver and the transmitter cannot use different trigger tables. Whichever selection is made last applies to both the RX and TX side.
FCR[5:4]: Transmit FIFO Trigger Select (requires EFR bit-4=1)
(logic 0 = default, TX trigger level = one) The FCTR Bits 6-7 are associated with these 2 bits by selecting one of the four tables. The 4 user selectable trigger levels in 4 tables are supported for compatibility reasons. These 2 bits set the trigger level for the transmit FIFO interrupt. The UART will issue a transmit interrupt when the number of characters in the FIFO falls below the selected trigger level, or when it gets empty in case that the FIFO did not get filled over the trigger level on last re-load. Table 14 below shows the selections.
FCR[3]: DMA Mode Select
This bit has no effect since TXRDY and RXRDY pins are not available in this device. It is provided for legacy software compatibility.
* Logic 0 = Set DMA to mode 0 (default). * Logic 1 = Set DMA to mode 1.
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is active.
* Logic 0 = No transmit FIFO reset (default). * Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is active.
* Logic 0 = No receive FIFO reset (default). * Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[0]: TX and RX FIFO Enable
* Logic 0 = Disable the transmit and receive FIFO (default). * Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
31
XR16V794
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE TABLE 14: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION
TRIGGER TABLE Table-A FCTR BIT-7 0 FCTR BIT-6 0 0 0 1 1 Table-B 0 1 0 1 0 1 0 0 1 1 0 0 1 1 Table-C 1 0 0 1 0 1 0 0 1 1 0 0 1 1 Table-D 1 1 X 0 1 0 1 X X X 0 1 0 1 8 16 56 60 Programmable Programmable 16L2752, 16L2750, via RXTRG via TXTRG 16C2852, 16C850, 16C854, 16C864 register register 0 1 0 1 8 16 24 28 8 16 32 56 16C654 FCR BIT-7 FCR BIT-6 FCR BIT-5 0 FCR
BIT-4
REV. 1.0.0
RECEIVE TRIGGER LEVEL
TRANSMIT TRIGGER LEVEL 1 (default)
COMPATIBILITY 16C550, 16C2550, 16C2552, 16C554, 16C580, 16L580
0 1 (default) 4 8 14
16 8 24 30
16C650A, 16L651
4.6
Line Control Register (LCR) - Read/Write
The Line Control Register is used to specify the asynchronous data communication format. The word or character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register.
LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL, DLM, DLD) enable.
* Logic 0 = Data registers are selected (default). * Logic 1 = Divisor latch registers (DLL, DLM and DLD) are selected.
LCR[6]: Transmit Break Enable
When enabled the Break control bit causes a break condition to be transmitted (the TX output is forced to a "space', logic 0, state). This condition remains until disabled by setting LCR bit-6 to a logic 0.
* Logic 0 = No TX break condition. (default) * Logic 1 = Forces the transmitter output (TX) to a "space", logic 0, for alerting the remote receiver of a line
break condition.
32
XR16V794
REV. 1.0.0
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR BIT-5 selects the forced parity format.
* LCR BIT-5 = logic 0, parity is not forced (default). * LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive
data.
* LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit is forced to a logical 0 for the transmit and receive
data.
TABLE 15: PARITY PROGRAMMING
LCR BIT-5 X 0 0 1 1 LCR BIT-4 X 0 1 0 1 LCR BIT-3 0 1 1 1 1 PARITY SELECTION No parity Odd parity Even parity Force parity to mark, "1" Forced parity to space, "0"
LCR[4]: TX and RX Parity Select
If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format.
* Logic 0 = ODD Parity is generated by forcing an odd number of logic 1's in the transmitted character. The
receiver must be programmed to check the same format (default).
* Logic 1 = EVEN Parity is generated by forcing an even the number of logic 1's in the transmitted character.
The receiver must be programmed to check the same format.
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data integrity check. See Table 15 above for parity selection summary.
* Logic 0 = No parity. * Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received.
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in conjunction with the programmed word length.
BIT-2 0 1 1 WORD
LENGTH
STOP BIT LENGTH (BIT TIME(S)) 1 (default) 1-1/2 2
5,6,7,8 5 6,7,8
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
BIT-1 0 0 1 1 BIT-0 0 1 0 1 WORD LENGTH 5 (default) 6 7 8
33
XR16V794
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE 4.7 Modem Control Register (MCR) - Read/Write
REV. 1.0.0
The MCR register is used for controlling the modem interface signals or general purpose inputs/outputs.
MCR[7]: Clock Prescaler Select (requires EFR bit-4=1)
* Logic 0 = Divide by one. The input clock from the crystal or external clock is fed directly to the Programmable
Baud Rate Generator without further modification, i.e., divide by one (default).
* Logic 1 = Divide by four. The prescaler divides the input clock from the crystal or external clock by four and
feeds it to the Programmable Baud Rate Generator, hence, data rates become one forth.
MCR[6]: Infrared Encoder/Decoder Enable (requires EFR bit-4=1)
The state of this bit depends on the sampled logic level of pin ENIR during power up, following a hardware reset (rising edge of RST# input). Afterward user can override this bit for desired operation.
* Logic 0 = Enable the standard modem receive and transmit character interface. * Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. While in this mode, the TX/RX output/
input are routed to the infrared encoder/decoder. The data input and output levels will conform to the IrDA infrared interface requirement. As such, while in this mode the infrared TX output will be a logic 0 during idle data conditions. FCTR bit-4 may be selected to invert the RX input signal level going to the decoder for infrared modules that provide rather an inverted output.
MCR[5]: Xon-Any Enable (requires EFR bit-4=1)
* Logic 0 = Disable Xon-Any function (default). * Logic 1 = Enable Xon-Any function. In this mode any RX character received will enable Xon, resume data
transmission.
MCR[4]: Internal Loopback Enable
* Logic 0 = Disable loopback mode (default). * Logic 1 = Enable local loopback mode, see loopback section and Figure 11.
MCR[3]: Send Char Immediate (OP2 in Local Loopback Mode)
This bit is used to transmit a character immediately irrespective of the bytes currently in the transmit FIFO. The data byte must be loaded into the transmit holding register (THR) immediately following the write to this bit (to set it to a '1'). In other words, no other register must be accessed between setting this bit and writing to the THR. The loaded byte will be transmitted ahead of all the bytes in the TX FIFO, immediately after the character currently being shifted out of the transmit shift register is sent out. The existing line parameters (parity, stop bits) will be used when composing the character. This bit is self clearing, therefore, must be set before sending a custom characer each time. Please note that the Transmitter must be enabled for this function (MSR[3] = 0). Also, if software flow control is enabled, the software flow control characters (Xon, Xoff) have higher priority and will get shifted out before the custom byte is transmitted.
* Logic 0 = Send Char Immediate disabled (default). * Logic 1 = Send Char Immediate enabled.
In Local Loopback Mode (MCR[4] = 1), this bit acts as the legacy OP2 output and controls the CD bit in the MSR register as shown in Figure 11. Please make sure that this bit is a '0' when exiting the Local Loopback Mode.
MCR[2]: DTR# or RTS# for Auto Flow Control (OP1 in Local Loopback Mode)
DTR# or RTS# auto hardware flow control select. This bit is in effect only when auto RTS/DTR is enabled by EFR bit-6. DTR# selection is associated with DSR# and RTS# is with CTS#.
* Logic 0 = Uses RTS# and CTS# pins for auto hardware flow control. * Logic 1 = Uses DTR# and DSR# pins for auto hardware flow control.
In Local Loopback mode (MCR[4] = 1), this bit acts as the legacy OP1 output and controls the RI bit in the MSR register, as shown in Figure 11.
34
XR16V794
REV. 1.0.0
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
MCR[1]: RTS# Output
The RTS# pin may be used for automatic hardware flow control by enabled by EFR bit-6 and MCR bit-2=0. If the modem interface is not used, this output may be used for general purpose.
* Logic 0 = Force RTS# output to a logic 1 (default). * Logic 1 = Force RTS# output to a logic 0.
MCR[0]: DTR# Output
The DTR# pin may be used for automatic hardware flow control enabled by EFR bit-6 and MCR bit-2=1. If the modem interface is not used, this output may be used for general purpose.
* Logic 0 = Force DTR# output to a logic 1 (default). * Logic 1 = Force DTR# output to a logic 0.
4.8 Line Status Register (LSR) - Read Only
This register provides the status of data transfers between the UART and the host. If IER bit-2 is set to a logic 1, an LSR interrupt will be generated immediately when any character in the RX FIFO has an error (parity, framing, overrun, break).
LSR[7]: Receive FIFO Data Error Flag
* Logic 0 = No FIFO error (default). * Logic 1 = An indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error or
break indication is in the FIFO data. This bit clears when there are no more errors in the FIFO.
LSR[6]: Transmitter Empty Flag
This bit is the Transmitter Empty indicator. This bit is set to a logic 1 whenever both the transmit FIFO (or THR, in non-FIFO mode) and the transmit shift register (TSR) are both empty. It is set to logic 0 whenever either the TX FIFO or TSR contains a data character.
LSR[5]: Transmit FIFO Empty Flag
This bit is the Transmit FIFO Empty indicator. This bit indicates that the transmitter is ready to accept a new character for transmission. This bit is set to a logic 1 when the last data byte is transferred from the transmit FIFO to the transmit shift register. The bit is reset to logic 0 as soon as a data byte is loaded into the transmit FIFO. In the non-FIFO mode this bit is set when the transmit holding register (THR) is empty; it is cleared when at a byte is written to the THR.
LSR[4]: Receive Break Flag
* Logic 0 = No break condition (default). * Logic 1 = The receiver received a break signal (RX was a logic 0 for one character frame time). In the FIFO
mode, only one break character is loaded into the FIFO. The break indication remains until the RX input returns to the idle condition, "mark" or logic 1.
LSR[3]: Receive Data Framing Error Flag
* Logic 0 = No framing error (default). * Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with
the character available for reading in RHR.
LSR[2]: Receive Data Parity Error Flag
* Logic 0 = No parity error (default). * Logic 1 = Parity error. The receive character in RHR (top of the FIFO) does not have correct parity
information and is suspect. This error is associated with the character available for reading in RHR.
35
XR16V794
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE LSR[1]: Receiver Overrun Flag
REV. 1.0.0
* Logic 0 = No overrun error (default). * Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens
when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into the FIFO, therefore the data in the FIFO is not corrupted by the error.
LSR[0]: Receive Data Ready Indicator
* Logic 0 = No data in receive holding register or FIFO (default). * Logic 1 = Data has been received and is saved in the receive holding register or FIFO.
4.9 Modem Status Register (MSR) - Read Only
This register provides the current state of the modem interface signals, or other peripheral device that the UART is connected. Lower four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a signal from the modem changes state. These bits may be used as general purpose inputs/outputs when they are not used with modem signals.
MSR[7]: CD Input Status
Normally this bit is the complement of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the MCR register. The CD# input may be used as a general purpose input when the modem interface is not used.
MSR[6]: RI Input Status
Normally this bit is the complement of the RI# input. In the loopback mode this bit is equivalent to bit-2 in the MCR register. The RI# input may be used as a general purpose input when the modem interface is not used.
MSR[5]: DSR Input Status
DSR# pin may function as automatic hardware flow control signal input if it is enabled and selected by Auto CTS/DSR bit (EFR bit-6=1) and RTS/DTR flow control select bit (MCR bit-2=1). Auto CTS/DSR flow control allows starting and stopping of local data transmissions based on the modem DSR# signal. A HIGH on the DSR# pin will stop UART transmitter as soon as the current character has finished transmission, and a LOW will resume data transmission. Normally MSR bit-5 is the complement of the DSR# input. However in the loopback mode, this bit is equivalent to the DTR# bit in the MCR register. The DSR# input may be used as a general purpose input when the modem interface is not used.
MSR[4]: CTS Input Status
CTS# pin may function as automatic hardware flow control signal input if it is enabled and selected by Auto CTS/DSR bit (EFR bit-6=1) and RTS/DTR flow control select bit (MCR bit-2=0). Auto CTS/DSR flow control allows starting and stopping of local data transmissions based on the modem CTS# signal. A HIGH on the CTS# pin will stop UART transmitter as soon as the current character has finished transmission, and a LOW will resume data transmission. Normally MSR bit-4 is the complement of the CTS# input. However in the loopback mode, this bit is equivalent to the RTS# bit in the MCR register. The CTS# input may be used as a general purpose input when the modem interface is not used.
MSR[3]: Delta CD# Input Flag
* Logic 0 = No change on CD# input (default). * Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem
status interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[2]: Delta RI# Input Flag
* Logic 0 = No change on RI# input (default). * Logic 1 = The RI# input has changed from a logic 0 to a logic 1, ending of the ringing signal. A modem status
interrupt will be generated if MSR interrupt is enabled (IER bit-3).
36
XR16V794
REV. 1.0.0
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
MSR[1]: Delta DSR# Input Flag
* Logic 0 = No change on DSR# input (default). * Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
MSR[0]: Delta CTS# Input Flag
* Logic 0 = No change on CTS# input (default). * Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
4.10 Modem Status Register (MSR) - Write Only
The upper four bits 7:4 of this register set the delay in number of bits time for the auto RS485 turn around from transmit to receive.
MSR [7:4]
When Auto RS485 feature is enabled (FCTR bit-5=1) and RTS# output is connected to the enable input of a RS-485 transceiver. These 4 bits select from 0 to 15 bit-time delay after the end of the last stop-bit of the last transmitted character. This delay controls when to change the state of RTS# output. This delay is very useful in long-cable networks. Table 16 shows the selection. The bits are enabled by EFR bit-4.
TABLE 16: AUTO RS485 HALF-DUPLEX DIRECTION CONTROL DELAY FROM TRANSMIT-TO-RECEIVE
MSR[7] 0 0 0 0 0 9 0 0 1 1 1 1 1 1 1 1 MSR[6] 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MSR[5] 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MSR[4] 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DELAY IN DATA BIT(S) TIME 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
37
XR16V794
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE MSR [3]: Transmitter Disable
REV. 1.0.0
This bit can be used to disable the transmitter by halting the Transmit Shift Register (TSR). When this bit is set to a '1', the bytes already in the FIFO will not be sent out. Also, any more data loaded into the FIFO will stay in the FIFO and will not be sent out. When this bit is set to a '0', the bytes currently in the TX FIFO will be sent out. Please note that setting this bit to a '1' stops any character from going out. Also, this bit must be a '0' for Send Char Immediate function (see MCR[3]).
* Logic 0 = Enable Transmitter (default). * Logic 1 = Disable Transmitter.
MSR [2]: Receiver Disable
This bit can be used to disable the receiver by halting the Receive Shift Register (RSR). When this bit is set to a '1', the receiver will not receive any more characters until it is enabled again by setting this bit to a '0'. Data currently in the RX FIFO can be read out. Please note that setting this bit to a '1' prevents any character from coming in.
* Logic 0 = Enable Receiver (default). * Logic 1 = Disable Receiver.
MSR [1:0]: Reserved 4.11 SCRATCH PAD REGISTER (SPR) - Read/Write
This is a 8-bit general purpose register for the user to store temporary data. The content of this register is preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.
4.12 FEATURE CONTROL REGISTER (FCTR) - Read/Write
This register controls the UART enhanced functions that are not available on ST16C554 or ST16C654.
FCTR[7:6]: TX and RX FIFO Trigger Table Select
These 2 bits select the transmit and receive FIFO trigger level table A, B, C or D. When table A, B, or C is selected the auto RTS flow control trigger level is set to "next FIFO trigger level" for compatibility to ST16C550 and ST16C650 series. RTS/DTR# triggers on the next level of the RX FIFO trigger level, in another word, one FIFO level above and one FIFO level below. See in Table 14 for complete selection with FCR bit 4-5 and FCTR bit 6-7, i.e. if Table C is used on the receiver with RX FIFO trigger level set to 56 bytes, RTS/DTR# output will de-assert at 60 and re-assert at 16.
FCTR[5]: Auto RS485 Enable
Auto RS485 half duplex control enable/disable.
* Logic 0 = Standard ST16C550 mode. Transmitter generates an interrupt when transmit holding register
(THR) becomes empty. Transmit Shift Register (TSR) may still be shifting data bit out.
* Logic 1 = Enable Auto RS485 half duplex direction control. RTS# output changes its logic level from HIGH to
LOW when finished sending the last stop bit of the last character out of the TSR register. It changes from LOW to HIGH when a data byte is loaded into the THR or transmit FIFO. The change to HIGH occurs prior sending the start-bit. It also changes the transmitter interrupt from transmit holding to transmit shift register (TSR) empty.
FCTR[4]: Infrared RX Input Logic Select
* Logic 0 = Select RX input as active HIGH encoded IrDA data, normal, (default). * Logic 1 = Select RX input as active LOW encoded IrDA data, inverted.
FCTR [3:0] - Auto RTS/DTR Flow Control Hysteresis Select
These bits select the auto RTS/DTR flow control hysteresis and only valid when TX and RX Trigger Table-D is selected (FCTR bit-6 and 7 are set to logic 1). The RTS/DTR hysteresis is referenced to the RX FIFO trigger level. After reset, these bits are set to logic 0 selecting the next FIFO trigger level for hardware flow control. Table 17 shows the 16 selectable hysteresis levels.
38
XR16V794
REV. 1.0.0
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE TABLE 17: 16 SELECTABLE HYSTERESIS LEVELS WHEN TRIGGER TABLE-D IS SELECTED
FCTR BIT-3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FCTR BIT-2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 FCTR BIT-1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FCTR BIT-0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 RTS/DTR HYSTERESIS (CHARACTERS) 0 +/- 4 +/- 6 +/- 8 +/- 8 +/- 16 +/- 24 +/- 32 +/- 12 +/- 20 +/- 28 +/- 36 +/- 40 +/- 44 +/- 48 +/- 52
4.13
Enhanced Feature Register (EFR) - Read/Write
Enhanced features are enabled or disabled using this register. Bits 3:0 provide single or dual consecutive character software flow control selection (see Table 18). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before programming a new setting.
EFR[7]: Auto CTS Flow Control Enable
Automatic CTS or DSR Flow Control.
* Logic 0 = Automatic CTS/DSR flow control is disabled (default). * Logic 1 = Enable Automatic CTS/DSR flow control. Transmission stops when CTS/DSR# pin de-asserts
(HIGH). Transmission resumes when CTS/DSR# pin is asserted (LOW). The selection for CTS# or DSR# is through MCR bit-2.
EFR[6]: Auto RTS or DTR Flow Control Enable
RTS#/DTR# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS/ DTR is selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and RTS/DTR# will de-assert (HIGH) at the next upper trigger or selected hysteresis level. RTS/DTR# will reassert (LOW) when FIFO data falls below the next lower trigger or selected hysteresis level (see FCTR bits 47). The RTS# or DTR# output must be asserted (LOW) before the auto RTS/DTR can take effect. The selection for RTS# or DTR# is through MCR bit-2. RTS/DTR# pin will function as a general purpose output when hardware flow control is disabled.
* Logic 0 = Automatic RTS/DTR flow control is disabled (default). * Logic 1 = Enable Automatic RTS/DTR flow control.
39
XR16V794
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE EFR[5]: Special Character Detect Enable
REV. 1.0.0
* Logic 0 = Special Character Detect Disabled (default). * Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with
data in Xoff-2 register. If a match exists, the received data will be transferred to FIFO and ISR bit-4 will be set to indicate detection of the special character. Bit-0 corresponds with the LSB bit for the receive character. If flow control is set for comparing Xon1, Xoff1 (EFR [1:0]=10) then flow control and special character work normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]=01) then flow control works normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special character interrupt.
EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables the enhanced functions in IER bits 7:5, ISR bits 5:4, FCR bits 5:4, MCR bits 7:5, 3:2 and MSR 7:2 bits to be modified. After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the new values. This feature prevents legacy software from altering or overwriting the enhanced functions once set. Normally, it is recommended to leave it enabled, logic 1.
* Logic 0 = modification disable/latch enhanced features. IER bits 7:5, ISR bits 5:4, FCR bits 5:4, MCR bits 7:5,
3:2 and MSR 7:2 bits are saved to retain the user settings. After a reset, all these bits are set to a logic 0 to be compatible with ST16C550 mode (default).
* Logic 1 = Enables the enhanced functions. When this bit is set to a logic 1 all enhanced features are
enabled.
EFR[3:0]: Software Flow Control Select
Combinations of software flow control can be selected by programming these bits, as shown in Table 18 below.
TABLE 18: SOFTWARE FLOW CONTROL FUNCTIONS
EFR BIT-3 0 0 1 0 1 X X X 1 EFR BIT-2 0 0 0 1 1 X X X 0 EFR BIT-1 0 X X X X 0 1 0 1 EFR BIT-0 0 X X X X 0 0 1 1 TRANSMIT AND RECEIVE SOFTWARE FLOW CONTROL No TX and RX flow control (default and reset) No transmit flow control Transmit Xon1, Xoff1 Transmit Xon2, Xoff2 Transmit Xon1 and Xon2, Xoff1 and Xoff2 No receive flow control Receiver compares Xon1, Xoff1 Receiver compares Xon2, Xoff2 Transmit Xon1, Xoff1 Receiver compares Xon1 or Xon2, Xoff1 or Xoff2 Transmit Xon2, Xoff2 Receiver compares Xon1 or Xon2, Xoff1 or Xoff2 Transmit Xon1 and Xon2, Xoff1 and Xoff2 Receiver compares Xon1 and Xon2, Xoff1 and Xoff2 No transmit flow control Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
0
1
1
1
1
1
1
1
0
0
1
1
40
XR16V794
REV. 1.0.0
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
4.14
TXCNT[7:0]: Transmit FIFO Level Counter - Read Only
Transmit FIFO level byte count from 0x00 (zero) to 0x40 (64). This 8-bit register gives an indication of the number of characters in the transmit FIFO. The FIFO level Byte count register is read only. The user can take advantage of the FIFO level byte counter for faster data loading to the transmit FIFO, which reduces CPU bandwidth requirements.
4.15 TXTRG [7:0]: Transmit FIFO Trigger Level - Write Only
An 8-bit value written to this register sets the TX FIFO trigger level from 0x00 (zero) to 0x40 (64). The TX FIFO trigger level generates an interrupt whenever the data level in the transmit FIFO falls below this preset trigger level.
4.16 RXCNT[7:0]: Receive FIFO Level Counter - Read Only
Receive FIFO level byte count from 0x00 (zero) to 0x40 (64). It gives an indication of the number of characters in the receive FIFO. The FIFO level byte count register is read only. The user can take advantage of the FIFO level byte counter for faster data unloading from the receiver FIFO, which reduces CPU bandwidth requirements.
4.17 RXTRG[7:0]: Receive FIFO Trigger Level - Write Only
An 8-bit value written to this register, sets the RX FIFO trigger level from 0x00 (zero) to 0x40 (64). The RX FIFO trigger level generates an interrupt whenever the receive FIFO level rises to this preset trigger level.
4.18 4.19 XOFF1, XOFF2, XON1 AND XON2 REGISTERS, WRITE ONLY XCHAR REGISTER, READ ONLY
These registers are used to program the Xoff1, Xoff2, Xon1 and Xon2 control characters respectively. This register gives the status of the last sent control character (xon or xoff) and the last received control character (xon or xoff). This register will be reset to 0x00 if, at anytime, the Software Flow Control is disabled.
XCHAR [7:4] : Reserved XCHAR [3]: Transmit Xon Indicator
If the last transmitted control character was a xon character or characters (xon1, xon2), this bit will be set to a logic 1. This bit will clear after the read.
XCHAR [2]: Transmit Xoff Indicator
If the last transmitted control character was a xoff character or characters (xoff1, xoff2), this bit will be set to a logic 1. This bit will clear after the read.
XCHAR [1]: Xon Detect Indicator
If the last received control character was a xon character or characters (xon1, xon2), this bit will be set to a logic 1. This bit will clear after the read.
XCHAR [0]: Xoff Detect Indicator
If the last received control character was a xoff character or characters (xoff1, xoff2), this bit will be set to a logic 1. This bit will clear after the read.
41
XR16V794
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE TABLE 19: UART RESET CONDITIONS
REGISTERS DLL DLM DLD RHR THR IER FCR ISR LCR MCR LSR MSR RESET STATE Bits 7-0 = 0x01 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0xXX Bits 7-0 = 0xXX Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x01 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x60 Bits 3-0 = logic 0 Bits 7-4 = logic levels of the inputs Bits 7-0 = 0xFF Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x00 I/O SIGNALS TX[ch-3:0] IRTX[ch-3:0] RTS#[ch-3:0] DTR#[ch-3:0] RESET STATE HIGH LOW HIGH HIGH
REV. 1.0.0
SPR FCTR EFR TFCNT TFTRG RFCNT RFTRG XCHAR XON1 XON2 XOFF1 XOFF2
42
XR16V794
REV. 1.0.0
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
ABSOLUTE MAXIMUM RATINGS
Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation Thermal Resistance (10x10x1.4mm 64-LQFP) 4 Volts -0.5 to 4V -40o to +85o C -65o to +150o C 500 mW -ja = 70C/W , -jc = 14C/W
ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS
TA=0o to 70oC (-40o to +85oC for industrial grade package), Vcc is 2.25V to 3.6V
SYMBOL VILCK VIHCK VIL VIH VOL VOH PARAMETER Clock input low level Clock input high level Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 1.8 IIL IIH CIN ICC Input Low Leakage Current Input High Leakage Current Input Pin Capacitance Power Supply Current -10 10 5 5 -10 10 5 5 2.5V MIN -0.3 1.8 -0.3 1.8 0.4 2.4 2.5V
MAX
3.3V MIN -0.3 2.4 -0.3 2.0
3.3
MAX
UNITS V V V V
CONDITIONS
0.6 4 0.5
0.6 6 0.7
0.4
V V V uA uA pF mA
IOL = 6mA IOH = -6mA IOH = -3mA
EXT Clock=2MHz A7-A0 at GND, all inputs at VCC or GND and outputs unloaded All UARTs asleep. A7A0 at GND, all inputs at VCC or GND and outputs unloaded.
ISLEEP
Sleep Current
60
60
uA
43
XR16V794
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE AC ELECTRICAL CHARACTERISTICS
REV. 1.0.0
TA=0o to 70oC (-40o to +85oC for industrial grade package), Vcc is 2.25V to 3.6V, 70 pF Load where applicable
SYMBOL TC1,TC2 TOSC TECK TAS TAH TCS TDY TRD TWR TRDV TWDS TRDH TWDH TADS TADH TRWS TRDA TRDH TWDS TWDH TRWH TCSL TCSD TWDO TMOD TRSI TSSI TRRI Clock Pulse Period Crystal Frequency External Clock Frequency Address Setup (16 Mode) Address Hold (16 Mode) Chip Select Width (16 Mode) Delay between CS# Active Cycles (16 Mode) Read Strobe Width (16 Mode) Write Strobe Width (16 Mode) Read Data Valid (16 Mode) Write Data Setup (16 Mode) Read Data Hold (16 Mode) Write Data Hold (16 Mode) Address Setup (68 Mode) Address Hold (68 Mode) R/W# Setup to CS# (68 Mode) Read Data Access (68 mode) Read Data Hold (68 mode) Write Data Setup (68 mode) Write Data Hold (68 Mode) CS# De-asserted to R/W# De-asserted (68 Mode) CS# Width (68 Mode) CS# Cycle Delay (68 Mode) Delay from IOW# to Modem Output Delay to set Interrupt from Modem Input Delay To Reset Interrupt From IOR# Delay From Stop To Set Interrupt Delay From IOR# To Reset Interrupt 10 7 1 25 25 50 50 50 1 45 7 3 3 3 20 15 10 7 1 25 25 50 50 50 1 45 10 15 7 3 3 3 20 15 3 3 25 25 25 20 20 10 15 PARAMETER 2.5V MIN 10 24 50 3 3 25 25 25 20 20 2.5V MAX 3.3V MIN 7 24 64 3.3V MAX UNITS ns MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Bclk ns
44
XR16V794
REV. 1.0.0
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
AC ELECTRICAL CHARACTERISTICS
TA=0o to 70oC (-40o to +85oC for industrial grade package), Vcc is 2.25V to 3.6V, 70 pF Load where applicable
SYMBOL TSI TWRI TRST Bclk PARAMETER Delay From Stop To Interrupt Delay From IOW# To Reset Interrupt Reset Pulse Baud Clock 40 2.5V MIN 2.5V MAX 45 45 40 16X or 8X of data rate 3.3V MIN 3.3V MAX 45 45 UNITS ns ns ns Hz
45
XR16V794
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE FIGURE 16. 16 MODE (INTEL) DATA BUS READ AND WRITE TIMING
REV. 1.0.0
A0-A7 TAS
Valid Address TAS
Valid Address
TAH
TCS
TAH
CS# TDY TRD IOR#
TRDV D0-D7 Valid Data
TRDH
TRDV Valid Data
TRDH
16Read
16 Mode (Intel) Data Bus Read Timing
A0-A7 TAS
Valid Address TAS
Valid Address
TAH
TCS
TAH
CS# TDY TWR IOW#
TWDS D0-D7 Valid Data
TWDH
TWDS Valid Data
TWDH
16Write
16 Mode (Intel) Data Bus Write Timing
46
XR16V794
REV. 1.0.0
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
FIGURE 17. 68 MODE (MOTOROLA) DATA BUS READ AND WRITE TIMING
A0-A7 TADS
Valid Address
Valid Address
TCSL
TADH
CS# TRWS TCSD
R/W#
TRWH
TRDH TRDA D0-D7 Valid Data Valid Data
68Read
68 Mode (Motorola) Data Bus Read Timing
A0-A7 TADS
Valid Address
Valid Address
TCSL
TADH
CS# TRWS TCSD
R/W#
TRWH
TWDS D0-D7
TWDH
Valid Data
Valid Data
68Write
68 Mode (Motorola) Data Bus Write Timing
47
XR16V794
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE FIGURE 18. MODEM INPUT/OUTPUT TIMING
IOW # Active T W DO RTS# DTR# Change of state Change of state
REV. 1.0.0
CD# CTS# DSR# T MOD INT
Change of state
Change of state
T MO D Active T RSI Active Active
IOR#
Active
Active
Active
T M OD RI# Change of state
FIGURE 19. RECEIVE INTERRUPT TIMING [NON-FIFO MODE]
RX
Start Bit Stop Bit
D0:D7
D0:D7
D0:D7
INT#
1 Byte in RHR
1 Byte in RHR
1 Byte in RHR
T RR
T RR
T RR
IO R#
(Reading data out of RHR)
48
XR16V794
REV. 1.0.0
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
FIGURE 20. TRANSMIT INTERRUPT TIMING [NON-FIFO MODE]
TX
(U n lo a d in g ) IE R [1 ] e n a b le d S ta rt B it S to p B it
D 0 :D 7
D 0 :D 7
D 0 :D 7
IS R is re a d
IS R is re a d
IS R is re a d
IN T # *
TW RI TW RI TW RI
IO W #
(L o a d in g d a ta in to T H R )
*T X in te rru p t is c le a re d w h e n th e IS R is re a d o r w h e n d a ta is lo a d e d in to th e T H R .
FIGURE 21. RECEIVE INTERRUPT TIMING [FIFO MODE]
Start Bit
RX
S D0:D7
S D0:D7 T
D0:D7
T SSI
S D0:D7 T
S D0:D7 T S D0:D7 T
S D0:D7 T
INT# RX FIFO fills up to RX Trigger Level or RX Data Tim eout
RX FIFO drops below RX Trigger Level
T RRI T RR
IOR#
(Reading data out of RX FIFO)
FIGURE 22. TRANSMIT INTERRUPT TIMING [FIFO MODE]
Start B it S top Bit Last Data B yte Transm itted S D 0:D 7 TS
TX FIFO Em pty
TX
(Unloading) IER [1] enabled
S
D 0:D 7 T
D 0:D 7 T
T SI
TS
D0:D 7 T S D 0:D 7 T
ISR is read
S
D 0:D 7 T
ISR is read
INT#*
TX FIFO fills up to trigger level
TW RI
TX FIFO drops below trigger level
IO W #
(Loading data into FIFO )
*TX interrupt is cleared when the ISR is read or when TX FIFO fills up to the trigger level.
49
XR16V794
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE PACKAGE DIMENSIONS 64 LEAD LOW-PROFILE QUAD FLAT PACK (10 x 10 x 1.4 mm LQFP)
D D1 48 33
REV. 1.0.0
49
32
D1
D
64
17
1
16
A2 e
B
A Seating Plane A1 L
C
Note: The control dimension is the millimeter column INCHES SYMBOL A A1 A2 B C D D1 e L MIN 0.055 0.002 0.053 0.007 0.004 0.465 0.390 MAX 0.063 0.006 0.057 0.011 0.008 0.480 0.398 MILLIMETERS MIN 1.40 0.05 1.35 0.17 0.09 11.80 9.90 MAX 1.60 0.15 1.45 0.27 0.20 12.20 10.10
0.020 BSC 0.018 0 0.030 7
0.50 BSC 0.45 0 0.75 7
50
XR16V794
REV. 1.0.0
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
REVISION HISTORY
REVISION A1.0.0 A1.0.1 P1.0.0 1.0.0 DATE June 2005 March 2006 October 2006 May 2007 Advanced Datasheet. Updated the 1.4mm-thick Quad Flat Pack package description from "TQFP" to "LQFP" to be consistent with JEDEC and Industry norms. Preliminary Datasheet. Final Datasheet. DESCRIPTION
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2007 EXAR Corporation Datasheet May 2007. Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
51
XR16V794
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
REV. 1.0.0
TABLE OF CONTENTS
GENERAL DESCRIPTION ................................................................................................ 1
APPLICATIONS............................................................................................................................................... 1 FEATURES .................................................................................................................................................... 1
FIGURE 1. BLOCK DIAGRAM ............................................................................................................................................................. 1 FIGURE 2. PIN OUT OF THE DEVICE.................................................................................................................................................. 2 ORDERING INFORMATION................................................................................................................................ 2
PIN DESCRIPTIONS ........................................................................................................ 3
1.0 DESCRIPTION ......................................................................................................................................... 6 2.0 FUNCTIONAL DESCRIPTIONS............................................................................................................... 6
2.1 DEVICE RESET ................................................................................................................................................... 6
2.1.1 HARDWARE RESET....................................................................................................................................................... 6 2.1.2 SOFTWARE RESET ....................................................................................................................................................... 6
2.2 UART CHANNEL SELECTION............................................................................................................................ 6
TABLE 1: UART CHANNEL SELECTION ............................................................................................................................................. 6
2.3 SIMULTANEOUS WRITE TO ALL CHANNELS ................................................................................................. 6 2.4 INT# OUPUT ........................................................................................................................................................ 7
TABLE 2: INT# PIN OPERATION FOR TRANSMITTER ........................................................................................................................... 7 TABLE 3: INT# PIN OPERATION FOR RECEIVER ................................................................................................................................ 7
2.5 CRYSTAL OSCILLATOR / BUFFER................................................................................................................... 7
FIGURE 3. TYPICAL OSCILLATOR CONNECTIONS................................................................................................................................. 7
2.6 PROGRAMMABLE BAUD RATE GENERATOR WITH FRACTIONAL DIVISOR.............................................. 8
FIGURE 4. BAUD RATE GENERATOR ................................................................................................................................................. 8 TABLE 4: TYPICAL DATA RATES WITH A 24 MHZ CRYSTAL OR EXTERNAL CLOCK AT 16X SAMPLING ..................................................... 9
2.7 TRANSMITTER .................................................................................................................................................... 9
2.7.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY ........................................................................................... 2.7.2 TRANSMITTER OPERATION IN NON-FIFO MODE .................................................................................................... FIGURE 5. TRANSMITTER OPERATION IN NON-FIFO MODE .............................................................................................................. 2.7.3 TRANSMITTER OPERATION IN FIFO MODE ............................................................................................................. FIGURE 6. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE ..................................................................................... 10 10 10 10 10
2.8 RECEIVER ......................................................................................................................................................... 11
2.8.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY .............................................................................................. 11 FIGURE 7. RECEIVER OPERATION IN NON-FIFO MODE .................................................................................................................... 11 FIGURE 8. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE ......................................................................... 12
2.9 THR AND RHR REGISTER LOCATIONS ......................................................................................................... 12
TABLE 5: TRANSMIT AND RECEIVE HOLDING REGISTER LOCATIONS, 16C550 COMPATIBLE ............................................................... 12
2.10 AUTO RTS/DTR HARDWARE FLOW CONTROL OPERATION.................................................................... 13
2.10.1 AUTO CTS/DSR FLOW CONTROL............................................................................................................................ 13 FIGURE 9. AUTO RTS/DTR AND CTS/DSR FLOW CONTROL OPERATION........................................................................................ 14
2.11 AUTO XON/XOFF (SOFTWARE) FLOW CONTROL...................................................................................... 14
TABLE 6: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL ............................................................................................................... 15
2.12 SPECIAL CHARACTER DETECT .................................................................................................................. 15 2.13 AUTO RS485 HALF-DUPLEX CONTROL ..................................................................................................... 15 2.14 INFRARED MODE ........................................................................................................................................... 15
FIGURE 10. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING .......................................................................... 16
2.15 SLEEP MODE WITH AUTO WAKE-UP.......................................................................................................... 17 2.16 INTERNAL LOOPBACK .................................................................................................................................. 18
FIGURE 11. INTERNAL LOOP BACK ................................................................................................................................................. 18
3.0 XR16V794 REGISTERS ........................................................................................................................ 18
FIGURE 12. THE XR16V794 REGISTERS........................................................................................................................................ 19
3.1 DEVICE CONFIGURATION REGISTER SET .................................................................................. 19
TABLE 7: XR16V794 REGISTER SETS ............................................................................................................................................ 19 TABLE 8: DEVICE CONFIGURATION REGISTERS ............................................................................................................................... 20 3.1.1 THE GLOBAL INTERRUPT SOURCE REGISTERS.................................................................................................... 20 3.1.1.1 INT0 CHANNEL INTERRUPT INDICATOR: ................................................................................................................ 21 3.1.1.2 INT1, INT2 AND INT3 INTERRUPT SOURCE LOCATOR ........................................................................................... 21 FIGURE 13. THE GLOBAL INTERRUPT REGISTERS, INT0, INT1, INT2 AND INT3 .............................................................................. 21 TABLE 9: UART CHANNEL [7:0] INTERRUPT SOURCE ENCODING AND CLEARING .............................................................................. 21 3.1.2 GENERAL PURPOSE 16-BIT TIMER/COUNTER [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (DEFAULT 0XXX-XX00-00).............................................................................................................................................................................. 22 3.1.2.1 TIMERMSB [7:0] AND TIMERLSB [7:0] ............................................................................................................. 22
I
XR16V794
REV. 1.0.0
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
3.1.2.2 TIMER [7:0] RESERVED....................................................................................................................................... 22 3.1.2.3 TIMERCNTL [7:0] REGISTER .............................................................................................................................. 22 TABLE 10: TIMER CONTROL COMMANDS ....................................................................................................................................... 22
TIMER OPERATION ................................................................................................................................................ 23
FIGURE 14. TIMER/COUNTER CIRCUIT............................................................................................................................................. 23 FIGURE 15. INTERRUPT OUTPUT IN ONE-SHOT AND RE-TRIGGERABLE MODES................................................................................. 23 3.1.3 8XMODE [7:0] (DEFAULT 0X00).................................................................................................................................. 24 3.1.4 REGA [7:0](DEFAULT 0X00) ....................................................................................................................................... 24 3.1.5 RESET [7:0] (DEFAULT 0X00)..................................................................................................................................... 24 3.1.6 SLEEP [7:0] ...................................................................................................................................... (DEFAULT 0X00) 24 3.1.7 DEVICE IDENTIFICATION AND REVISION................................................................................................................. 24 3.1.7.1 DVID [7:0] (DEFAULT 0X48) ................................................................................................................................. 25 3.1.7.2 DREV [7:0] (DEFAULT (0X01) .............................................................................................................................. 25 3.1.8 REGB [7:0] ....................................................................................................................................... (DEFAULT 0X00) 25
3.2 UART CHANNEL CONFIGURATION REGISTERS.......................................................................................... 26
TABLE 11: UART CHANNEL CONFIGURATION REGISTERS. .................................................................................................. 26 TABLE 12: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED BY EFR BIT-4. ....... 27
4.0 INTERNAL REGISTER DESCRIPTIONS .............................................................................................. 28
4.1 RECEIVE HOLDING REGISTER (RHR) - READ ONLY ................................................................................... 28 4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY ............................................................................... 28 4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE ................................................................................ 28
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................... 28 4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION.................................................................. 28
4.4 INTERRUPT STATUS REGISTER (ISR) - READ ONLY .................................................................................. 30
4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 30 4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. 30 TABLE 13: INTERRUPT SOURCE AND PRIORITY LEVEL ..................................................................................................................... 30
4.5 FIFO CONTROL REGISTER (FCR) - WRITE ONLY......................................................................................... 31
TABLE 14: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION .......................................................................... 32
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE ........................................................................................ 32
TABLE 15: PARITY PROGRAMMING ................................................................................................................................................. 33
4.7 MODEM CONTROL REGISTER (MCR) - READ/WRITE .................................................................................. 4.8 LINE STATUS REGISTER (LSR) - READ ONLY.............................................................................................. 4.9 MODEM STATUS REGISTER (MSR) - READ ONLY ....................................................................................... 4.10 MODEM STATUS REGISTER (MSR) - WRITE ONLY....................................................................................
34 35 36 37
TABLE 16: AUTO RS485 HALF-DUPLEX DIRECTION CONTROL DELAY FROM TRANSMIT-TO-RECEIVE ................................................. 37
4.11 SCRATCH PAD REGISTER (SPR) - READ/WRITE ....................................................................................... 38 4.12 FEATURE CONTROL REGISTER (FCTR) - READ/WRITE ........................................................................... 38
TABLE 17: 16 SELECTABLE HYSTERESIS LEVELS WHEN TRIGGER TABLE-D IS SELECTED ................................................................ 39
4.13 ENHANCED FEATURE REGISTER (EFR) - READ/WRITE ........................................................................... 39
TABLE 18: SOFTWARE FLOW CONTROL FUNCTIONS ........................................................................................................................ 40
4.14 TXCNT[7:0]: TRANSMIT FIFO LEVEL COUNTER - READ ONLY ................................................................ 4.15 TXTRG [7:0]: TRANSMIT FIFO TRIGGER LEVEL - WRITE ONLY ............................................................... 4.16 RXCNT[7:0]: RECEIVE FIFO LEVEL COUNTER - READ ONLY................................................................... 4.17 RXTRG[7:0]: RECEIVE FIFO TRIGGER LEVEL - WRITE ONLY .................................................................. 4.18 XOFF1, XOFF2, XON1 AND XON2 REGISTERS, WRITE ONLY................................................................... 4.19 XCHAR REGISTER, READ ONLY ..................................................................................................................
41 41 41 41 41 41
TABLE 19: UART RESET CONDITIONS ...................................................................................................................................... 42
ABSOLUTE MAXIMUM RATINGS ................................................................................. 43 ELECTRICAL CHARACTERISTICS............................................................................... 43
DC ELECTRICAL CHARACTERISTICS............................................................................................................. 43 AC ELECTRICAL CHARACTERISTICS............................................................................................................. 44
FIGURE 16. 16 MODE (INTEL) DATA BUS READ AND WRITE TIMING ................................................................................................. FIGURE 17. 68 MODE (MOTOROLA) DATA BUS READ AND WRITE TIMING ........................................................................................ FIGURE 18. MODEM INPUT/OUTPUT TIMING .................................................................................................................................... FIGURE 19. RECEIVE INTERRUPT TIMING [NON-FIFO MODE]........................................................................................................... FIGURE 20. TRANSMIT INTERRUPT TIMING [NON-FIFO MODE]......................................................................................................... FIGURE 21. RECEIVE INTERRUPT TIMING [FIFO MODE]................................................................................................................... FIGURE 22. TRANSMIT INTERRUPT TIMING [FIFO MODE]................................................................................................................. 46 47 48 48 49 49 49
REVISION HISTORY ..................................................................................................................................... 51 TABLE OF CONTENTS ..................................................................................................... I
II

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